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TLC32045CFNR PDF预览

TLC32045CFNR

更新时间： 2024-11-30 21:20:07
品牌 Logo 应用领域
德州仪器 - TI PC电信电信集成电路
页数 文件大小 规格书
39页 523K
描述
PCM CODEC, PQCC28

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TLC32045CFNR 技术参数

生命周期：Obsolete包装说明：QCCJ,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.83滤波器：YES
JESD-30 代码：S-PQCC-J28长度：11.5062 mm
负电源额定电压：-5 V功能数量：1
端子数量：28工作模式：SYNCHRONOUS/ASYNCHRONOUS
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装形状：SQUARE封装形式：CHIP CARRIER
认证状态：Not Qualified座面最大高度：4.57 mm
最大压摆率：40 mA标称供电电压：5 V
表面贴装：YES技术：CMOS
电信集成电路类型：PCM CODEC温度等级：COMMERCIAL
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD宽度：11.5062 mm
Base Number Matches：1

TLC32045CFNR 数据手册

 浏览型号TLC32045CFNR的Datasheet PDF文件第2页浏览型号TLC32045CFNR的Datasheet PDF文件第3页浏览型号TLC32045CFNR的Datasheet PDF文件第4页浏览型号TLC32045CFNR的Datasheet PDF文件第5页浏览型号TLC32045CFNR的Datasheet PDF文件第6页浏览型号TLC32045CFNR的Datasheet PDF文件第7页 
TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I  
VOICE-BAND ANALOG INTERFACE CIRCUITS  
SLAS017F − MARCH 1988 − REVISED MAY 1995  
†
D
D
D
D
D
14-Bit Dynamic Range ADC and DAC  
J OR N PACKAGE  
(TOP VIEW)  
2’s Complement Format  
Variable ADC and DAC Sampling Rate Up  
to 19,200 Samples per Second  
NU  
RESET  
EODR  
NU  
1
28  
27  
26  
25  
24  
NU  
2
Switched-Capacitor Antialiasing Input Filter  
and Output-Reconstruction Filter  
IN+  
3
FSR  
IN−  
4
DR  
AUX IN+  
Serial Port for Direct Interface to  
TMS(SMJ)320C17, TMS(SMJ)32020,  
TMS(SMJ)320C25,  
5
MSTR CLK  
VDD  
6
23 AUX IN−  
7
22  
21  
20  
19  
18  
17  
16  
15  
OUT+  
OUT−  
VCC+  
and TMS320C30 Digital Signal Processors  
8
REF  
9
DGTL GND  
SHIFT CLK  
EODX  
D
D
Synchronous or Asynchronous ADC and  
DAC Conversion Rates With Programmable  
Incremental ADC and DAC Conversion  
Timing Adjustments  
10  
11  
12  
13  
14  
VCC−  
ANLG GND  
ANLG GND  
NU  
DX  
WORD/BYTE  
FSX  
Serial Port Interface to SN74(54)299  
Serial-to-Parallel Shift Register for Parallel  
Interface to TMS(SMJ)32010,  
TMS(SMJ)320C15, or Other Digital  
Processors  
NU  
†
Refer to the mechanical data for the JT package.  
FK OR FN PACKAGE  
(TOP VIEW)  
D
D
Internal Reference for Normal Operation  
and External Purposes, or Can Be  
Overridden by External Reference  
CMOS Technology  
4
3
2
1 28 27 26  
DR  
5
6
7
8
9
25  
24 AUX IN+  
IN−  
description  
MSTR CLK  
VDD  
23  
22  
21  
20  
19  
AUX IN−  
OUT+  
OUT−  
VCC+  
The TLC32044 and TLC32045 are complete  
REF  
analog-to-digital and digital-to-analog input and  
output systems on single monolithic CMOS chips.  
The TLC32044 and TLC32045 integrate a  
bandpass switched-capacitor antialiasing input  
filter, a 14-bit-resolution A/D converter, four  
microprocessor-compatible serial port modes, a  
14-bit-resolution D/A converter, and a low-pass  
switched-capacitor output-reconstruction filter.  
The devices offer numerous combinations of  
master clock input frequencies and conversion/  
sampling rates, which can be changed via digital  
processor control.  
DGTL GND  
SHIFT CLK  
EODX  
10  
11  
VCC−  
12 13 14 15 16 17 18  
NU − Nonusable; no external connection should be made to  
these terminals (see Table 2).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...39

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