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TL4810BN PDF预览

TL4810BN

更新时间: 2024-11-21 21:11:55
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 驱动信息通信管理光电二极管接口集成电路
页数 文件大小 规格书
7页 107K
描述
Vacuum Fluorescent Driver, 10-Segment, BICMOS, PDIP18, DIP-18

TL4810BN 技术参数

生命周期:Contact Manufacturer包装说明:DIP-18
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.65
数据输入模式:SERIAL显示模式:DOT MATRIX
接口集成电路类型:VACUUM FLUORESCENT DISPLAY DRIVERJESD-30 代码:R-PDIP-T18
JESD-609代码:e0长度:22.48 mm
复用显示功能:NO功能数量:1
区段数:10端子数量:18
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
座面最大高度:5.08 mm最大供电电压:15.75 V
最小供电电压:4.75 V标称供电电压:5 V
电源电压1-最大:60 V电源电压1-分钟:5 V
表面贴装:NO技术:BICMOS
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL宽度:7.62 mm
Base Number Matches:1

TL4810BN 数据手册

 浏览型号TL4810BN的Datasheet PDF文件第2页浏览型号TL4810BN的Datasheet PDF文件第3页浏览型号TL4810BN的Datasheet PDF文件第4页浏览型号TL4810BN的Datasheet PDF文件第5页浏览型号TL4810BN的Datasheet PDF文件第6页浏览型号TL4810BN的Datasheet PDF文件第7页 
TL4810B, TL4810BI  
VACUUM FLUORESCENT DISPLAY DRIVERS  
SLDS006C – DECEMBER 1984 – REVISED MAY 1993  
N PACKAGE  
(TOP VIEW)  
Each Device Drives Ten Lines  
60-V Output Voltage Rating  
40-mA Output Source Current  
High-Speed Serially-Shifted Data Input  
CMOS-Compatible Inputs  
Q8  
Q9  
1
2
3
4
5
6
7
8
9
18  
17  
16  
15  
14  
Q7  
Q10  
Q6  
SERIAL DATA OUT  
CLOCK  
V
CC2  
Latches on All Driver Outputs  
GND  
DATA IN  
Improved Direct Replacement for  
UCN4810A and TL4810A  
VCC1  
13 BLANKING  
12  
11  
10  
LATCH ENABLE (STROBE)  
Q1  
Q2  
Q3  
Q5  
Q4  
description  
The TL4810B and TL4810BI are monolithic  
BIDFET integrated circuits designed to drive a  
DW PACKAGE  
(TOP VIEW)  
dot matrix or segmented vacuum fluorescent  
display (VFD). These devices feature a serial data  
output to cascade additional devices for large  
display arrays.  
Q8  
Q7  
Q9  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
Q10  
Q6  
NC  
A 10-bit data word is serially loaded into the shift  
register on the positive-going transitions of the  
clock. Parallel data is transferred to the output  
buffers through a 10-bit D-type latch while LATCH  
ENABLE is high and is latched when LATCH  
ENABLE is low. When BLANKING is high, all  
outputs are low.  
CLOCK  
GND  
NC  
SERIAL DATA OUT  
V
CC2  
15 DATA IN  
14  
13  
12  
11  
V
BLANKING  
CC1  
LATCH ENABLE (STROBE)  
Q1  
Q2  
Q3  
Q5  
Q4  
Outputs are totem-pole structures formed by npn  
emitter-follower and double-diffused MOS  
(DMOS) transistors with output voltage ratings of  
70 V and 40-mA source-current capability. All  
inputs are compatible with CMOS and TTL levels,  
but each requires the addition of a pullup resistor  
NCNo internal connection  
to V  
when driven by TTL logic.  
CC1  
The TL4810B is characterized for operation from  
0°C to 70°C. The TL4810BI is characterized for  
operation from 40°C to 85°C.  
BIDFET – Bipolar, double-diffused, N-channel and P-channel MOS transistors on same chip. This is a patented process.  
Copyright 1993, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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