Datasheet > THC63LVD103

THC63LVD103

更新时间： 2022-12-16 16:07:23

品牌	Logo	应用领域
THINE		/
页数	文件大小	规格书
12页	102K
描述
135MHz 30Bits COLOR LVDS Transmitter

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THC63LVD103 数据手册

THC63LVD103 _Rev2.2

THC63LVD103

135MHz 30Bits COLOR LVDS Transmitter

General Description

Features

The THC63LVD103 transmitter is designed to support

pixel data transmission between Host and Flat Panel

Display from NTSC up to SXGA+ resolutions.

•

Wide dot clock range: 8-135MHz suited for NTSC,

VGA, SVGA, XGA,SXGA and SXGA+

•

PLL requires no external components

Supports spread spectrum clock generator

On chip jitter filtering

The THC63LVD103 converts 35bits of CMOS/TTL

data into LVDS(Low Voltage Differential Signaling)

data stream. The transmitter can be programmed for ris-

ing edge or falling edge clocks through a dedicated pin.

At a transmit clock frequency of 135MHz, 30bits of

RGB data and 5bits of timing and control data

(HSYNC, VSYNC, DE, CNTL1, CNTL2) are transmit-

ted at an effective rate of 945Mbps per LVDS channel.

Clock edge selectable

Supports reduced swing LVDS for low EMI

Power down mode

Low power single 3.3V CMOS design

64pin TQFP

Backward compatible with

THC63LVDM63R(18bits) / M83R(24bits)

Block Diagram

CMOS/TTL INPUT

LVDS OUTPUT

TA0-6

TA +/-

TB +/-

TC +/-

TD +/-

TE +/-

TB0-6

TC0-6

TD0-6

TE0-6

TCLK +/-

CLK IN

PLL

(8 to 135MHz)

(8 to135MHz)

R/F

/PDWN

THine Electronics, Inc.

12 3 4 5 6 7...12

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