Datasheet > THC63LVD104S

THC63LVD104S

更新时间： 2024-01-01 03:14:07

品牌	Logo	应用领域
THINE		/
页数	文件大小	规格书
12页	143K
描述
112MHz 30Bits Color LVDS Receiver

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技术参数
数据手册

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THC63LVD104S 技术参数

生命周期：	Contact Manufacturer	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.55
Base Number Matches：	1

THC63LVD104S 数据手册

THC63LVD104S Rev.1.0

THC63LVD104S

112MHz 30Bits Color LVDS Receiver

General Description

Features

The THC63LVD104S receiver is designed to support

pixel data transmission between Host and Flat Panel

Display from NTSC up to SXGA resolutions. The

THC63LVD104S converts the LVDS data streams back

into 35bits of CMOS/TTL data with rising edge or fall-

ing edge clock for convenient with a variety of LCD

panel controllers.At a transmit clock frequency of

112MHz, 30bits of RGB data and 5bits of timing and

control data (HSYNC,VSYNC,DE,CNTL1,CNTL2)

are transmitted at an effective rate of 784Mbps per

LVDS channel.Using a 112MHz clock, the data

throughput is 490Mbytes per second.

•

Wide dot clock range: 8-112MHz suited for NTSC,

VGA, SVGA, XGA, and SXGA

•

PLL requires no external components

50% output clock duty cycle

TTL clock edge and position programmable(3 step)

Power down mode

Low power single 2.5V CMOS design

TQFP 64pin

Pin compatible with THC63LVD104A

Fail-safe for Open CLK Input

Block Diagram

LVDS INPUT

CMOS/TTL OUTPUT

RA+/-

RA6-RA0

RB6-RB0

RB+/-

RC+/-

RC6-RC0

RD+/-

RE+/-

RD6-RD0

RE6-RE0

PLL

RCLK+/-

CLKOUT

(8 to112MHz)

CMOS/TTL INPUT

R/F

THine Electronics, Inc.

12 3 4 5 6 7...12

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