THC63LVDM83R/THC63LVDM63R_Rev2.0
THC63LVDM83R/THC63LVDM63R
REDUCED SWING LVDS 24Bit/18Bit COLOR HOST-LCD PANEL INTERFACE
General Description
Features
The THC63LVDM83R transmitter converts 28bits of
CMOS/TTL data into LVDS (Low Voltage Differential
Signaling) data stream. A phase-locked transmit clock
is transmitted in parallel with the data streams over a
fifth LVDS link. At a transmit clock frequency of
85MHz, 28bits of RGB data and 4bits of LCD timing
and control data (HSYNC, VSYNC, CNTL1, CNTL2)
are transmitted at a rate of 595Mbps per LVDS channel.
Also available is THC63LVDM63R that converts 21bits
of CMOS/TTL data into LVDS(Low Voltage Differen-
tial Signaling) data stream. Both transmitters can be
programmed reduced swing LVDS through a dedicated
pin for low power consumption and EMI.
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28:4 Data channel compression at up to
298 Megabytes per sec throughput
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Wide dot clock range: 20-85MHz suited for VGA,
SVGA, XGA and SXGA
Narrow bus (10 lines or 8 lines) reduces cable size
Support Reduced swing LVDS for Low EMI
200mV swing LVDS/350mV swing LVDS
selectable
Support Spread Spectrum Clock Generator
On chip Input Jitter Filtering
PLL requires No external components
Single 3.3V supply with 125mW(TYP)
Power-Down Mode
Low profile 56 or 48 Lead TSSOP Package
Clock Edge Programmable
Improved Replacement for the National DS90C383
or DS90C363
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Block Diagram
THC63LVDM83R
THC63LVDM63R
DATA
CMOS/TTL
INPUTS
DATA
CMOS/TTL
INPUTS
(LVDS)
(LVDS)
7
7
7
TA0-6
TA +/-
TA0-6
TB0-6
TC0-6
TD0-6
TA +/-
TB +/-
TC +/-
TD +/-
7
7
TB0-6
TC0-6
TB +/-
TC +/-
7
7
(140-595Mbit/On Each
LVDS Channel)
(140-595Mbit/On Each
LVDS Channel)
TRANSMITTER
CLOCK IN
TRANSMITTER
CLOCK IN
(20 to 85MHz)
R/F
TCLK +/-
PLL
PLL
TCLK +/-
(20 to 85MHz)
CLOCK
(LVDS)
CLOCK
(LVDS)
R/F
20-85MHz
20-85MHz
/PDWN
RS
/PDWN
RS
Copyright 2001-2003 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.