Datasheet > THC63LVD104

THC63LVD104

更新时间： 2024-01-29 06:17:51

品牌	Logo	应用领域
THINE		/
页数	文件大小	规格书
13页	87K
描述
90MHz 30Bits COLOR LVDS Receiver

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技术参数
数据手册

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THC63LVD104 技术参数

生命周期：	Contact Manufacturer	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.55
Base Number Matches：	1

THC63LVD104 数据手册

THine

THC63LVD104A Rev.1.0

THC63LVD104A

90MHz 30Bits COLOR LVDS Receiver

General Description

Features

•

Wide dot clock range: 8-90MHz suited for NTSC,

VGA, SVGA, XGA, and WXGA

The THC63LVD104A receiver is designed to support

pixel data transmission between Host and Flat Panel

Display from NTSC up to WXGA resolutions. The

THC63LVD104A converts the LVDS data streams back

into 35bits of CMOS/TTL data with rising edge or fall-

ing edge clock for convenient with a variety of LCD

panel controllers.At a transmit clock frequency of

90MHz, 30bits of RGB data and 5bits of timing and

control data (HSYNC,VSYNC,DE,CNTL1,CNTL2)

are transmitted at an effective rate of 630Mbps per

LVDS channel.Using a 90MHz clock, the data through-

put is 394Mbytes per second.

•

PLL requires no external components

50% output clock duty cycle

TTL clock edge programmable

Power down mode

Low power single 3.3V CMOS design

64pin TQFP

Backward compatible with THC63LVDF64x

(18bits) / F84x(24bits)

Block Diagram

LVDS INPUT

CMOS/TTL OUTPUT

RA+/-

RA6-RA0

RB+/-

RC+/-

RB6-RB0

RC6-RC0

RD+/-

RE+/-

RD6-RD0

RE6-RE0

PLL

RCLK+/-

(8 to90MHz)

CLKOUT

CMOS/TTL INPUT

TEST

R/F

THine Electronics, Inc.

12 3 4 5 6 7...13

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