Datasheet > TH74KB27AVWKRNGS

TH74KB27AVWKRNGS

更新时间： 2023-02-26 14:14:11

品牌	Logo	应用领域
爱特美尔 - ATMEL		/
页数	文件大小	规格书
20页	1122K
描述
CCD Sensor, 2.50V, Square, Surface Mount, CERAMIC, J LEAD PACKAGE-84

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TH74KB27AVWKRNGS 数据手册

TH7426A/27A

PIN DESCRIPTION

Odd and Even channels are fully independent, therefore same pin function will be found on odd and even sides.

This is the preload injection stage electrical input. Each Φ

pulse down overfills preload storage capacitance with

electrons. Φ

is connected to a diode cathode which anode is internally tied to Vss.

This is the preload stage skimming gate. Its bias determines the voltage up to which preload storage capacitance

will be biased. Thus it drives preload level.

GL1

GL2

This is the storage capacitance grid bias. It determines the bottom voltage of preload storing well, while V

deter-

GL1

mines its top level. Preload capacitance thus is charged up proportionately to (V

- V

) bias difference.

GL2

GL1

This is the main register storage grid clock. Charges are stored under Φ

when transfer is disabled (RE at low le-

vel).

is also used for lateral transfers to input nodes.

This is the main register transfer grid clock. Φ is used to isolate

content during lateral transfers. The main re-

gister is beginning and ending with

RE input, it is internally pulled down when RE is low, preventing transfers, preload injection, read out and isolating

each well.

which therefore controls main register access and outputs.

is gated by

This is the “Read Enable” input. When high, it allows Φ

input connection to main register, when low, main register

corresponding grids are pulled down whatever

input level is.

This input helps to serially read out two or more multiplexors with one single

the main register as long as RE is low, thus read out can occur later on.

signal for all. Data are stored into

This is the lateral transfer grid command. Lateral transfer is allowed when

input nodes, all photodiode information is collected at the same time.

is at high level.

is common to all

This is the lateral input stage skimming grid bias. This grid determines photodiodes reset bias, always the same

from integration time to integration time. After photodiode reset (input node capacitance reset) extra charges leading

to overcrossing V

level are skimmed back into Φ main register wells.

This is the InGaAs photodiode common cathode bias. V is available on odd and ev en side, however, both pins are

connected together, to photodiode substrate.

This is main register output grid bias. It is used to isolate read out capacitance from main register. It allows charges

to be read out when Φ is at low level.

This is the read out capacitance reset bias. After each single read out, read out capacitance is cleared off (reset) to

level, during

clock high state.

5/20

1 2 3 456 7 8...20

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与TH74KB27AVWKRNGS相关器件

型号	品牌	描述	获取价格	数据表
TH74KB27AVWKRPG	ATMEL	CCD Sensor, 2.50V, Square, Surface Mount, CERAMIC, J LEAD PACKAGE-84	获取价格
TH74KB27AVWKRPGB/T	ATMEL	CCD Sensor, 2.50V, Square, Surface Mount, CERAMIC, J LEAD PACKAGE-84	获取价格
TH74KB27AVWKRPGD/T	ATMEL	CCD Sensor, 2.50V, Square, Surface Mount, CERAMIC, J LEAD PACKAGE-84	获取价格
TH74KB27AVWKRPGS	ATMEL	CCD Sensor, 2.50V, Square, Surface Mount, CERAMIC, J LEAD PACKAGE-84	获取价格
TH74KB27AVWKSG	ATMEL	CCD Sensor, 2.50V, Square, Surface Mount, CERAMIC, J LEAD PACKAGE-84	获取价格
TH74KB27AVWKSGB/T	ATMEL	CCD Sensor, 2.50V, Square, Surface Mount, CERAMIC, J LEAD PACKAGE-84	获取价格

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