TCR13AGADJ
Attention in Use
● Capacitors(Output, Input, and Bias Capacitor)
Ceramic capacitors can be used for these devices. However, because of the type of the capacitors, there might be unexpected
thermal features. Please consider application condition for selecting capacitors. For stable operation, please use over 4.7 μF
input capacitor, 1.0 μF bias capacitor and 4.7 μF output ceramic capacitor.
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Mounting
The long distance between IC and each capacitor might affect phase compensation by impedance in wire and inductor. For
stable power supply, output capacitor need to mount near IC as much as possible. Also V and GND pattern need to be
IN
large and make the wire impedance small as possible.
Permissible Loss
Please have enough design patterns for expected maximum permissible loss. And under consideration of ambient
temperature, input voltage, and output current etc, we recommend proper dissipation ratings for maximum permissible loss;
in general maximum dissipation rating is 70 to 80 percent.
Overcurrent Protection and Thermal shutdown
Overcurrent protection and Thermal shutdown are designed in these products, but these are not designed to constantly
ensure the suppression of the device within operation limits. Depending on the condition during actual usage, it could affect
the electrical characteristic specification and reliability. Also note that if output pins and GND pins are not completely shorted
out, these products might break down.
When using these products, please read through and understand the concept of dissipation for absolute maximum ratings
from the above mention or our ‘Semiconductor Reliability Handbook’. Then use these products under absolute maximum
ratings in any condition. Furthermore, Toshiba recommends inserting failsafe system into the design.
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Adjustable output voltage type
TCR13AGADJ is adjustable output voltage type. V
is the output voltage control pin, please refer to example of application
circuit and reference resistance table. Please select the tolerance of the resistance value in accordance by the system. In
ADJ
addition, please assemble R1 and R2 to minimize common impedance. For V
assembly,
ADJ
please design PCB pattern as short as possible to avoid noise effect.
© 2017 - 2022
Toshiba Electronic Devices & Storage Corporation
2022-03-25
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