TCR13AGADJ
Application Note
1. Example of Application Circuit
V
BIAS
GND
V
BIAS
R
2
OFF/ON
1.0 μF
CONTROL
V
ADJ
R
1
(CFB = 10 nF)
V
OUT
V
IN
LOAD
4.7 μF
4.7 μF
The figure above shows the recommended configuration for using a Low-Dropout regulator. Please connect over 4.7μF
capacitor at V and V pins, and over 1μF capacitor at V pin, as close as possible to each pins for stable input/output
IN OUT BIAS
operation. (Ceramic capacitors can be used). But simple usage of large input capacitance is known to form unwanted LC
resonance in combination with input wire inductance. So please check parameter with the actual device and circuit.
C
is optional capacitance that improve Transient response, Output noise, Oscillation resistance, PSRR and
FB
Overshoot. However, it does not necessarily need.
is the output voltage control pin. Typical V
V
ADJ
value is 0.5 V. For best performance R1 and R2 should have
ADJ
similar temperature coefficients, otherwise output voltage accuracy will be compromised.
ꢇ1
ꢀꢁꢂꢃ = ꢀ × �1 +
ꢈ
ꢄꢅꢆ
ꢇ2
Reference resistance table
This is reference data. Please check parameter with the actual device and circuit.
Output voltage (typ.)
R1
R2
0.6 V
0.7 V
0.8 V
0.9 V
1.0 V
1.1 V
1.2 V
1.3 V
1.8 V
3.6 V
4 kΩ
20 kΩ
20 kΩ
20 kΩ
20 kΩ
20 kΩ
20 kΩ
20 kΩ
20 kΩ
20 kΩ
20 kΩ
8 kΩ
12 kΩ
16 kΩ
20 kΩ
24 kΩ
28 kΩ
32 kΩ
52 kΩ
124 kΩ
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Toshiba Electronic Devices & Storage Corporation
2022-03-25
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