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TC7SP3125TU(TE85L,F) PDF预览

TC7SP3125TU(TE85L,F)

更新时间： 2024-11-25 04:30:35
品牌 Logo 应用领域
东芝 - TOSHIBA 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
11页 286K
描述
IC,BUFFER/DRIVER,SINGLE,1-BIT,CMOS,FP,6PIN,PLASTIC

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TC7SP3125TU(TE85L,F) 技术参数

是否Rohs认证： 符合生命周期：Not Recommended
包装说明：DFP, FL6,.07,25Reach Compliance Code：unknown
风险等级：5.79控制类型：ENABLE LOW
JESD-30 代码：R-PDFP-F6负载电容（CL）：30 pF
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.003 A
位数：1功能数量：1
端子数量：6最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：DFP封装等效代码：FL6,.07,25
封装形状：RECTANGULAR封装形式：FLATPACK
包装方法：TAPE AND REEL电源：1.2/2.5,1.8/3.3 V
Prop。Delay @ Nom-Sup：30 ns认证状态：Not Qualified
子类别：Bus Driver/Transceivers表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：FLAT端子节距：0.635 mm
端子位置：DUALBase Number Matches：1

TC7SP3125TU(TE85L,F) 数据手册

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TC7SP3125TU/WBG  
TOSHIBA Digital Integrated Circuit Silicon Monolithic  
TC7SP3125TU,TC7SP3125WBG  
Low Voltage / Low Power 1-Bit Dual Supply Bus Buffer  
The TC7SP3125 is an advanced high-speed CMOS 1-bit dual  
supply voltage interface bus buffer fabricated with silicon gate  
CMOS technology.  
TC7SP3125TU  
It is also designed with over voltage tolerant inputs and  
outputs up to 3.6 V.  
Designed for use as an interface between a 1.2-V, 1.5-V, 1.8-V,  
or 2.5-V bus and a 1.8-V, 2.5-V or 3.3-V bus in mixed 1.2-V,  
1.5-V, 1.8-V or 2.5-V/1.8-V, 2.5-V or 3.3-V supply systems.  
The A-input interfaces with the 1.2-V, 1.5-V, 1.8-V or 2.5-V  
bus, the B-output with the 1.8-V, 2.5-V, 3.3-V bus.  
The enable input ( OE ) can be used to disable the device so  
that the signal lines are effectively isolated.  
UF6  
All inputs are equipped with protection circuits against static  
discharge or transient excess voltage.  
TC7SP3125WBG  
S-WFBGA6-0102-0.40A01  
Weight  
UF6:  
S-WFBGA6-0102-0.40A01:  
0.007 g (typ.)  
0.001 g (typ.)  
Features (Note)  
•
Level converter for interfacing 1.2-V to 1.8-V, 1.2-V to 2.5-V, 1.2-V to 3.3-V, 1.5-V to 2.5-V, 1.5-V to 3.3-V, 1.8-V  
to 2.5-V, 1.8-V to 3.3-V or 2.5-V to 3.3-V system.  
•
High-speed operation : t = 6.8 ns (max) (V  
= 2.5 ± 0.2 V, V  
= 1.8 ± 0.15 V, V  
= 3.3 ± 0.3 V)  
pd  
CCA  
CCA  
CCA  
CCA  
CCB  
t
pd  
t
pd  
t
pd  
t
pd  
t
pd  
t
pd  
t
pd  
= 7.8 ns (max) (V  
= 8.6 ns (max) (V  
= 3.3 ± 0.3 V)  
CCB  
= 1.5 ± 0.1 V, V  
= 3.3 ± 0.3 V)  
= 3.3 ± 0.3 V)  
CCB  
CCB  
= 22 ns (max) (V  
= 9.5 ns (max) (V  
= 1.2 ± 0.1 V, V  
= 1.8 ± 0.15 V, V  
= 2.5 ± 0.2 V)  
= 2.5 ± 0.2 V)  
CCA  
CCB  
CCB  
= 10.5 ns (max) (V  
= 1.5 ± 0.1 V, V  
CCA  
= 23 ns (max) (V  
= 30 ns (max) (V  
= 1.2 ± 0.1 V, V  
= 1.2 ± 0.1 V, V  
= 2.5 ± 0.2 V)  
= 1.8 ± 0.15 V)  
CCA  
CCA  
CCB  
CCB  
•
Output current : I  
/ I  
= ±12 mA (min) (V  
= 3.0 V)  
OHB OLB  
CCB  
I
I
/ I  
= ±9mA (min) (V  
= ±3 mA (min) (V  
= 2.3 V)  
= 1.65 V)  
OHB OLB  
CCB  
/ I  
OHB OLB  
CCB  
•
•
Latch-up performance: -300 mA  
ESD performance:Machine model ≥ ±200 V  
Human body model ≥ ±2000 V  
•
•
Ultra-small package: UF6, WCSP6  
Low current consumption: Using the new circuit significantly reduces current consumption when OE = “H”.  
Suitable for battery-driven applications such as PDAs and cellular phones.  
•
•
Floating A-bus is permitted. (when OE = “H”)  
3.6-V tolerant function and power-down protection provided on all inputs and outputs.  
Note: Do not apply a signal to any bus pins when it is in the output mode. Damage may result.  
1
2009-02-02  
1234567...11

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