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TC7MPS3125FK(EL) PDF预览

TC7MPS3125FK(EL)

更新时间： 2024-11-29 21:21:27
品牌 Logo 应用领域
东芝 - TOSHIBA 光电二极管
页数 文件大小 规格书
23页 317K
描述
IC,BUS TRANSCEIVER,DUAL,1/3-BIT,CMOS,TSSOP,16PIN,PLASTIC

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TC7MPS3125FK(EL) 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：TSSOP, TSSOP16,.16,20Reach Compliance Code：unknown
风险等级：5.92控制类型：COMMON CONTROL
计数方向：BIDIRECTIONALJESD-30 代码：R-PDSO-G16
负载电容（CL）：15 pF最大I（ol）：0.003 A
位数：3功能数量：2
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP16,.16,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源：1.2/2.5,1.8/3.3 VProp。Delay @ Nom-Sup：61 ns
认证状态：Not Qualified子类别：Bus Driver/Transceivers
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
Base Number Matches：1

TC7MPS3125FK(EL) 数据手册

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TC7MPS3125FK/FTG  
TOSHIBA Digital Integrated Circuit Silicon Monolithic  
TC7MPS3125FK,TC7MPS3125FTG  
Low Voltage/Low Power 1 + 3-Bit Dual Supply Bus Transceiver  
The TC7MPS3125FK/FTG is a dual supply, advanced  
high-speed CMOS 4-bit dual supply voltage interface bus  
TC7MPS3125FK  
transceiver fabricated with silicon gate CMOS technology.  
It is also designed with over voltage tolerant inputs and  
outputs up to 3.6 V.  
Designed for use as an interface between a 1.2-V, 1.5-V, 1.8-V,  
or 2.5-V bus and a 1.8-V, 2.5-V or 3.6-V bus in mixed 1.2-V, 1.5-V,  
1.8-V or 2.5-V/1.8-V, 2.5-V or 3.6-V supply systems.  
The A-port interfaces with the 1.2-V, 1.5-V, 1.8-V or 2.5-V bus,  
the B-port with the 1.8-V, 2.5-V, 3.3-V bus.  
The direction of data transmission is determined by the level of  
the DIR input. The enable input (OE) can be used to disable the  
TC7MPS3125FTG  
device so that the buses are effectively isolated. (Note1)  
All inputs are equipped with protection circuits against static  
discharge or transient excess voltage.  
Features  
•
Bidirectional interface between 1.2-V and 1.8-V, 1.2-V and  
2.5-V, 1.2-V and 3.3-V, 1.5-V and 2.5-V, 1.5-V and 3.3-V, 1.8-V  
and 2.5-V, 1.8-V and 3.3-V or 2.5-V and 3.3-V buses.  
Weight  
•
High-speed operation: t = 6.8 ns (max) (V  
= 2.5 ± 0.2 V,  
pd  
CCA  
VSSOP16-P-0030-0.50: 0.02 g (typ.)  
VQON16-P-0303-0.50: 0.013 g (typ.)  
V
CCB  
= 3.3 ± 0.3 V)  
t
pd  
= 8.9 ns (max) (V  
= 1.8 ± 0.15 V,  
CCA  
V
CCB  
= 3.3 ± 0.3 V)  
t
t
t
t
t
t
= 10.3 ns (max) (V  
= 1.5 ± 0.1 V, V = 3.3 ± 0.3 V)  
CCB  
pd  
pd  
pd  
pd  
pd  
pd  
CCA  
= 61 ns (max) (V  
= 1.2 ± 0.1 V, V  
= 3.3 ± 0.3 V)  
CCA  
CCB  
= 9.5 ns (max) (V  
= 1.8 ± 0.15 V, V  
= 2.5 ± 0.2 V)  
= 2.5 ± 0.2 V)  
CCA  
CCB  
= 10.8 ns (max) (V  
= 1.5 ± 0.1 V, V  
CCA  
CCB  
= 60 ns (max) (V  
= 58 ns (max) (V  
= 1.2 ± 0.1 V, V  
= 1.2 ± 0.1 V, V  
= 3.0 V)  
= 2.5 ± 0.2 V)  
= 1.8 ± 0.15 V)  
CCA  
CCA  
CCB  
CCB  
•
Output current: I /I  
= ±12 mA (min) (V  
OH OL CC  
I
I
I
/I  
= ±9mA (min) (V  
= 2.3 V)  
= 1.65 V)  
= 1.4 V)  
OH OL  
CC  
/I  
= ±3 mA (min) (V  
OH OL  
CC  
CC  
/I  
= ±1mA (min) (V  
OH OL  
•
•
Latch-up performance: ±300 mA  
ESD performance:Machine model ≥ ±200 V  
Human body model ≥ ±2000 V  
•
•
Ultra-small package: VSSOP (US16), VQON16  
Low current consumption: Using the new circuit significantly reduces current consumption when OE = “H”.  
Suitable for battery-driven applications such as PDAs and cellular phones.  
•
•
Floating A-bus and B-bus are permitted. (when OE = “H”)  
3.6-V tolerant function and power-down protection provided on all inputs and outputs.  
Note 1: Do not apply a signal to any bus pins when it is in the output mode. Damage may result.  
Note: When mounting VQON package, the type of recommended flux is RA or RMA.  
1
2011-07-21  
1234567...23

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