Datasheet > TC7MET138AFK_07

TC7MET138AFK_07

更新时间： 2024-11-23 04:00:27

品牌	Logo	应用领域
东芝 - TOSHIBA		/
页数	文件大小	规格书
6页	187K
描述
3-to-8 Line Decoder

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TC7MET138AFK_07 数据手册

TC7MET138AFK

TOSHIBA CMOS Didital Integrated Circuit Silicon Monolithic

TC7MET138AFK

3-to-8 Line Decoder

The TC7MET138AFK is an advanced high speed CMOS 3-to-8

line decoder fabricated with silicon gate C MOS technology. It

achieves the high speed operation similar to equivalent bipolar

schottky TTL while maintaining the CMOS low power

dissipation.

When the device is enabled, 3 binary select inputs (A, B and C)

determine which one of the outputs (Y0 - Y7) will go low.

When enable input G1 is held low or either G2A or G2B is held

high, decoding function is inhibited and all outputs go high. G1,

G2A, and G2B inputs are provided to ease cascade connection

and for use as an address decoder for memory systems.

The input voltage are compatible with TTL output voltage.

This device may be used as a level converter for interfacing 3.3

V to 5 V system.

Weight: 0.02 g (typ.)

Input protection and output circuit ensure that 0 to 5.5 V can be applied to the input and output ^(Note)pins

without regard to the supply voltage. These structure prevents device destruction due to mismatched supply and

input/output voltages such as battery back up, hot board insertion, etc.

Note: V

= 0 V

Features

•

High speed: t = 7.6 ns (typ.) (V

= 5 V)

Low power dissipation: I

= 4 μA (max) (Ta = 25°C)

Compatible with TTL outputs: V = 0.8 V (max)

= 2.0 V (min)

•

Power down protection is provided on all inputs and outputs.

Balanced propagation delays: t ≈ t

pLH

pHL

Pin and function compatible with the 74 series (74AC/HC/ALS/LS etc.) 138 type.

2007-10-19

12 3 4 5 6

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