Datasheet > TC7MA2373FK_07

TC7MA2373FK_07

更新时间： 2024-11-05 03:24:27

品牌	Logo	应用领域
东芝 - TOSHIBA		锁存器
页数	文件大小	规格书
11页	229K
描述
Low-Voltage Octal D-Type Latch with 3.6 V Tolerant Inputs and Outputs

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TC7MA2373FK_07 数据手册

TC7MA2373FK

TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic

TC7MA2373FK

Low-Voltage Octal D-Type Latch with 3.6 V Tolerant Inputs and Outputs

The TC7MA2373FK is a high performance CMOS octal D-type

latch. Designed for use in 1.8 V, 2.5 V or 3.3 V systems, it

achieves high speed operation while maintaining the CMOS low

power dissipation.

It is also designed with over voltage tolerant inputs and

outputs up to 3.6 V.

This 8 bit D-type latch is controlled by a latch enable input

(LE) and output enable input (OE).

When the OE input is high, the eight outputs are in a high

impedance state.

The 26 Ω series resistor helps reducing output overshoot and

Weight: 0.03 g (typ.)

undershoot without external resistor.

All inputs are equipped with protection circuits against static discharge.

Features

•

26 Ω series resistors on outputs.

Low voltage operation: V = 1.8~3.6 V

High speed operation: t = 5.1 ns (max) (V

= 3.0~3.6 V)

= 2.3~2.7 V)

= 1.8 V)

= 6.1 ns (max) (V

= 9.8 ns (max) (V

•

3.6 V tolerant inputs and outputs.

Output current: I /I = ±12 mA (min) (V

= 3.0 V)

OH OL

= ±8 mA (min) (V

= 2.3 V)

= 1.8 V)

OH OL

= ±4 mA (min) (V

OH OL

•

Latch-up performance: −300 mA

ESD performance:Machine model ≥ ±200 V

Human body model ≥ ±2000 V

Package: VSSOP (US)

•

Power down protection is provided on all inputs and outputs.

Supports live insertion/withdrawal (*)

*: To ensure the high-impedance state during power up or power down, OE should be tied to V

through a

pullup resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

2007-10-19

12 3 4 5 6 7...11

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