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TC74VHC74F_07 PDF预览

TC74VHC74F_07

更新时间: 2024-12-01 05:15:55
品牌 Logo 应用领域
东芝 - TOSHIBA 触发器
页数 文件大小 规格书
10页 261K
描述
Dual D-Type Flip-Flop with Preset and Clear

TC74VHC74F_07 数据手册

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TC74VHC74F/FN/FT/FK  
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic  
TC74VHC74F,TC74VHC74FN,TC74VHC74FT,TC74VHC74FK  
Dual D-Type Flip-Flop with Preset and Clear  
Note: The JEDEC SOP (FN) is not available in  
Japan.  
The TC74VHC74 is an advanced high speed CMOS D-FLIP  
FLOP fabricated with silicon gate C2MOS technology.  
TC74VHC74F  
It achieves the high speed operation similar to equivalent  
Bipolar Schottky TTL while maintaining the CMOS low power  
dissipation.  
The signal level applied to the D INPUT is transferred to Q  
OUTPUT during the positive going transition of the CK pulse.  
CLR and PR are independent of the CK and are  
accomplished by setting the appropriate input low.  
An input protection circuit ensures that 0 to 5.5 V can be  
applied to the input pins without regard to the supply voltage.  
This device can be used to interface 5 V to 3 V systems and two  
supply systems such as battery back up. This circuit prevents  
device destruction due to mismatched supply and input voltages.  
TC74VHC74FN  
TC74VHC74FT  
TC74VHC74FK  
Features  
High speed: f  
= 170 MHz (typ.) at V  
= 5 V  
max  
CC  
Low power dissipation: I  
= 2 μA (max) at Ta = 25°C  
CC  
High noise immunity: V  
= V  
= 28% V  
(min)  
NIH  
NIL  
CC  
Power down protection is provided on all inputs.  
Balanced propagation delays: t  
t
pHL  
pLH  
Wide operating voltage range: V  
= 2 V to 5.5 V  
CC (opr)  
Pin and function compatible with 74ALS74  
Weight  
SOP14-P-300-1.27A  
SOL14-P-150-1.27  
: 0.18 g (typ.)  
: 0.12 g (typ.)  
TSSOP14-P-0044-0.65A : 0.06 g (typ.)  
VSSOP14-P-0030-0.50  
: 0.02 g (typ.)  
1
2007-10-01  

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