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TC74VHC175FK_12 PDF预览

TC74VHC175FK_12

更新时间: 2024-11-17 01:17:35
品牌 Logo 应用领域
东芝 - TOSHIBA /
页数 文件大小 规格书
10页 229K
描述
Quad D-Type Flip Flop with Clear

TC74VHC175FK_12 数据手册

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TC74VHC175F/FT/FK  
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic  
TC74VHC175F,TC74VHC175FT,TC74VHC175FK  
Quad D-Type Flip Flop with Clear  
TC74VHC175F  
TC74VHC175FT  
TC74VHC175FK  
The TC74VHC175 is an advanced high speed CMOS QUAD  
D-TYPE FLIP FLOP fabricated with silicon gate C2MOS  
technology.  
It achieves the high speed operation similar to equivalent  
Bipolar Schottky TTL while maintaining the CMOS low power  
dissipation.  
These four flip-flops are controlled by a clock input (CK) and a  
clear input (CLR ).  
The information data applied to the D inputs (D1 thru D4) are  
transferred to the outputs (Q1 thru Q4 and Q1 thru Q4 ) on the  
positive-going edge of the clock pulse.  
When the CLR input is held low, the Q outputs are at the low  
logic level and the Q outputs are at the high logic level,  
regardless of other input conditions.  
An input protection circuit ensures that 0 to 5.5 V can be  
applied to the input pins without regard to the supply voltage.  
This device can be used to interface 5 V to 3 V systems and two  
supply systems such as battery back up. This circuit prevents  
device destruction due to mismatched supply and input voltages.  
Features  
High speed: f  
= 210 MHz (typ.) at V  
= 5 V  
max  
CC  
Low power dissipation: I  
= 4 μA (max) at Ta = 25°C  
CC  
High noise immunity: V  
= V  
= 28% V  
(min)  
NIH  
NIL  
CC  
Power down protection is provided on all inputs.  
Balanced propagation delays: t  
t
pHL  
pLH  
Wide operating voltage range: V  
= 2 to 5.5 V  
CC (opr)  
Low noise: V  
= 0.8 V (max)  
OLP  
Pin and function compatible with 74ALS175  
Weight  
SOP16-P-300-1.27A  
: 0.18 g (typ.)  
TSSOP16-P-0044-0.65A : 0.06 g (typ.)  
VSSOP16-P-0030-0.50  
: 0.02 g (typ.)  
1
2012-02-29  

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