Datasheet > TC74LVX138F_07

TC74LVX138F_07

更新时间： 2024-11-24 04:49:35

品牌	Logo	应用领域
东芝 - TOSHIBA		/
页数	文件大小	规格书
9页	249K
描述
3-to-8 Line Decoder

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中文翻译

获取价格

数据手册

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TC74LVX138F_07 数据手册

TC74LVX138F/FN/FT

TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic

TC74LVX138F,TC74LVX138FN,TC74LVX138FT

3-to-8 Line Decoder

Note: xxxFN (JEDEC SOP) is not available in

Japan.

The TC74LVX138F/ FN/ FT is a high-speed CMOS 3-to-8 line

decoder fabricated with silicon gate CMOS technology. Designed

TC74LVX138F

for use in 3-V systems, it achieves high-speed operation while

maintaining the CMOS low power dissipation.

This device is suitable for low-voltage and battery operated

systems.

When the device is enabled, 3 Binary Select inputs (A, B and

C) determine which one of the outputs ( Y0 - Y7 ) will go low.

When enable input G1 is held low or either G2A or G2B is

held high, decoding function is inhibited and all outputs go high.

G1, G2A , and G2B inputs are provided to ease cascade

TC74LVX138FN

connection and for use as an address decoder for memory

systems.

An input protection circuit ensures that 0 to 5.5V can be

applied to the input pins without regard to the supply voltage.

This device can be used to interface 5V to 3V systems and two

supply systems such as battery back up. This circuit prevents

device destruction due to mismatched supply and input voltages.

Features

TC74LVX138FT

•

High-speed: t = 5.5 ns (typ.) (V

= 3.3 V)

Low power dissipation: I

= 4 μA (max) (Ta = 25°C)

Input voltage level: V = 0.8 V (max) (V

= 3 V)

= 2.0 V (min) (V

•

Power-down protection provided on all inputs

∼

−

Balanced propagation delays: t

pHL

pLH

Pin and function compatible with 74HC138

Weight

SOP16-P-300-1.27A

SOL16-P-150-1.27

TSSOP16-P-0044-0.65A

: 0.18 g (typ.)

: 0.12 g (typ.)

: 0.06 g (typ.)

2007-10-17

12 3 4 5 6 7...9

中文翻译

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