Datasheet > TC74HCT74AP_07

TC74HCT74AP_07

更新时间： 2024-11-15 05:04:07

品牌	Logo	应用领域
东芝 - TOSHIBA		触发器
页数	文件大小	规格书
8页	309K
描述
Dual D-Type Flip Flop with Preset and Clear

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中文翻译

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数据手册

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TC74HCT74AP_07 数据手册

TC74HCT74AP/AF/AFN

TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic

TC74HCT74AP,TC74HCT74AF,TC74HCT74AFN

Dual D-Type Flip Flop with Preset and Clear

Note: xxxFN (JEDEC SOP) is not available in

Japan.

The TC74HCT74A is a high speed CMOS D FLIP FLOP

fabricated with silicon gate C²MOS technology.

TC74HCT74AP

It achieves the high speed operation similar to equivalent

LSTTL while maintaining the CMOS low power dissipation.

This device may be used as a level converter for interfacing

TTL or NMOS to High Speed CMOS. The inputs are compatible

with TTL , NMOS and CMOS output voltage levels.

The signal level applied to the D INPUT is transferred to Q

OUTPUT during the positive going transition of the CLOCK

pulse.

CLEAR and PRESET are independent of the CLOCK and

are accomplished by setting the applopriate input to an “L” level.

TC74HCT74AF

All inputs are equipped with protection circuits against static

discharge or transient excess voltage.

Features

•

High speed: f

= 53 MHz (typ.) at V

= 5 V

max

Low power dissipation: I

= 2 μA (max) at Ta = 25°C

Compatible with TTL outputs: V = 2 V (min)

TC74HCT74AFN

= 0.8 V (max)

•

Wide interfacing ability: LSTTL, NMOS, CMOS

Output drive capability: 10 LSTTL loads

Symmetrical output impedance: |I | = I

= 4 mA (min)

∼

−

Balanced propagation delays: t

pHL

pLH

Pin and function compatible with 74LS74

Pin Assignment

Weight

DIP14-P-300-2.54

SOP14-P-300-1.27A

SOL14-P-150-1.27

: 0.96 g (typ.)

: 0.18 g (typ.)

: 0.12 g (typ.)

2007-10-01

12 3 4 5 6 7 8

中文翻译

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