Datasheet > TC74HC74AP_07

TC74HC74AP_07

更新时间： 2024-11-25 05:04:07

品牌	Logo	应用领域
东芝 - TOSHIBA		触发器
页数	文件大小	规格书
10页	313K
描述
CMOS Digital Integrated Circuit Silicon Monolithic Dual D-Type Flip Flop Preset and Clear

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中文翻译

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数据手册

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TC74HC74AP_07 数据手册

TC74HC74AP/AF/AFN

TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic

TC74HC74AP,TC74HC74AF,TC74HC74AFN

Dual D-Type Flip Flop Preset and Clear

Note: xxxFN (JEDEC SOP) is not available in

Japan.

The TC74HC74A is a high speed CMOS D FLIP FLOP

fabricated with silicon gate C²MOS technology.

TC74HC74AP

It achieves the high speed operation similar to equivalent

LSTTL while maintaining the CMOS low power dissipation.

The signal level applied to the D INPUT is transferred to Q

OUTPUT during the positive going transition of the CLOCK

pulse.

CLEAR and PRESET are independent of the CLOCK and

are accomplished by setting the appropriate input to an “L” level.

All inputs are equipped with protection circuits against static

discharge or transient excess voltage.

TC74HC74AF

Features

•

High speed: f

= 77 MHz (typ.) at V

= 5 V

max

Low power dissipation: I

= 2 μA (max) at Ta = 25°C

High noise immunity: V

= V

= 28% V

(min)

NIH

NIL

Output drive capability: 10 LSTTL loads

Symmetrical output impedance: |I | = I

= 4 mA (min)

TC74HC74AFN

∼

−

Balanced propagation delays: t

pHL

pLH

Wide operating voltage range: V

(opr) = 2~6 V

Pin and function compatible with 74LS74

Pin Assignment

Weight

DIP14-P-300-2.54

SOP14-P-300-1.27A

SOL14-P-150-1.27

: 0.96 g (typ.)

: 0.18 g (typ.)

: 0.12 g (typ.)

2007-10-01

12 3 4 5 6 7...10

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