Datasheet > TC74HC280AP_07

TC74HC280AP_07

更新时间： 2024-11-16 05:04:11

品牌	Logo	应用领域
东芝 - TOSHIBA		/
页数	文件大小	规格书
9页	336K
描述
9-Bit Parity Generator/Checker

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中文翻译

获取价格

数据手册

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TC74HC280AP_07 数据手册

TC74HC280AP/AF

TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic

TC74HC280AP,TC74HC280AF

9-Bit Parity Generator/Checker

The TC74HC280A is a high speed CMOS 9-BIT PARITY

GENERATOR fabricated with silicon gate C²MOS technology.

It achieves the high speed operation similar to equivalent

LSTTL while maintaining the CMOS low power dissipation.

The TC74HC280A is composed of nine data inputs A thru I and

odd/even parity outputs Σ ODD and Σ EVEN.

TC74HC280AP

The odd parity output is high when an odd number of data

inputs are high. The even parity output is high when an even

number of data inputs are high.

The word-length capability is easily expanded by cascading.

All inputs are equipped with protection circuits against static

discharge or transient excess voltage.

TC74HC280AF

Features

•

High speed: t = 22 ns (typ.) at V

= 5 V

Low power dissipation: I

= 4 μA (max) at Ta = 25°C

High noise immunity: V

= V

= 28% V

(min)

NIH

NIL

Output drive capability: 10 LSTTL loads

Symmetrical output impedance: |I | = I

= 4 mA (min)

Weight

DIP14-P-300-2.54

SOP14-P-300-1.27A

∼

−

Balanced propagation delays: t

pHL

pLH

: 0.96 g (typ.)

: 0.18 g (typ.)

Wide operating voltage range: V

(opr) = 2 to 6 V

Pin and function compatible with 74LS280

Pin Assignment

NC: No connection

2007-10-01

12 3 4 5 6 7...9

中文翻译

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