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TC74HC125AP_07 PDF预览

TC74HC125AP_07

更新时间: 2024-11-16 05:04:11
品牌 Logo 应用领域
东芝 - TOSHIBA /
页数 文件大小 规格书
9页 280K
描述
Quad Bus Buffer

TC74HC125AP_07 数据手册

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TC74HC125AP/AF/AFN,126AP/AF  
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic  
TC74HC125AP,TC74HC125AF,TC74HC125AFN  
TC74HC126AP,TC74HC126AF  
TC74HC125AP/AF/AFN Quad Bus Buffer  
TC74HC126AP/AF Quad Bus Buffer  
Note: xxxFN (JEDEC SOP) is not available in  
Japan.  
TC74HC125AP, TC74HC126AP  
TC74HC125AF, TC74HC126AF  
TC74HC125AFN  
The TC74HC125A/126A are high speed CMOS QUAD BUS  
BUFFERs fabricated with silicon gate C2MOS technology.  
They achieve the high speed operation similar to equivalent  
LSTTL while maintaining the CMOS low power dissipation.  
The TC74HC125A requires the 3-state control input G to be  
set high to place the output into the high impedance state,  
whereas the TC74HC126A requires the control input to be set  
low to place the output into high impedance.  
All inputs are equipped with protection circuits against static  
discharge or transient excess voltage.  
Features  
High speed: t = 10 ns (typ.) at V  
= 5 V  
pd  
CC  
Low power dissipation: I  
= 4 μA (max) at Ta = 25°C  
CC  
High noise immunity: V  
= V  
= 28% V  
(min)  
NIH  
NIL  
CC  
Output drive capability: 15 LSTTL loads  
Symmetrical output impedance: |I | = I  
= 6 mA (min)  
OL  
OH  
Balanced propagation delays: t  
t
pHL  
pLH  
Wide operating voltage range: V  
(opr) = 2 to 6 V  
CC  
Pin and function compatible with 74LS125/126  
Weight  
DIP14-P-300-2.54  
SOP14-P-300-1.27A  
SOL14-P-150-1.27  
: 0.96 g (typ.)  
: 0.18 g (typ.)  
: 0.12 g (typ.)  
1
2007-10-01  

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