Datasheet > TB501-01

TB501-01

更新时间： 2024-12-01 03:28:59

品牌	Logo	应用领域
PLL		测试
页数	文件大小	规格书
1页	29K
描述
Test Board for PLL501-01/-05

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TB501-01 数据手册

TB501-01/-05

Test Board for PLL501-01/-05

This note documents the test board prepared for the PLL501-01 and PLL501-05

The test board is designed to simplify the testing of the PLL501-01 and PLL501-05, and implements the best approaches for

decoupling the VCXO chip using discrete external components.

While this test board achieves satisfactory decoupling results, best results are achieved when the VCXO chip is laid out into

the final PCB, following the recommendations indicated in the data sheet.

1. External Components and Layout Recommendations (as per PLL501-01/-05 data sheet)

The PLL501-01/-05 requires a minimum number of external components for proper operation. A standard low frequency

decoupling capacitor of 4.7mF or more should be used between VDD and GND (pin 2 and pin 4, as well as pin 6 and pin 7).

Additionally, higher frequency decoupling capacitors of 0.1mF are required between VDD and GND (between pin 2 and 4,

and between pin 6 and 7). These higher frequency decoupling capacitors must be connected as close to the PLL501-01/-05

chip as possible, and preferably directly next to the PLL501-01/-05 pins. A series termination resistor of 33W may be used

for the clock output (series termination resistor not implemented on test board).

The input crystal must be connected as close to the chip as possible, and preferably directly next to the PLL501-01/-05

pins. If a crystal with C_Lhigher than 10pF is used, it will requires additional loading capacitors externally to

complement the internal 10pF of the PLL501-01/-05: one between each crystal electrode and GND, as close to the

crystal as possible, and preferably directly next to the crystal electrodes. Consult PhaseLink for recommended suppliers.

2. Crystal Specifications (as per PLL501-01/-05 data sheet)

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP. MAX.

UNITS

Crystal Resonator Frequency

Crystal Loading Capacitance Rating

Crystal Pullability

F_XIN

C_L(xtal)

C₀/C₁(xtal)

R_E

Parallel Fundamental Mode

MHz

AT cut

250

Recommended ESR

+3.3V

3. Test board schematic

XTAL, NSK 17.664 MHz, 14 pF

4.7 uf

17.664 MHz

Note: C5 and C4 are only

required if a crystal

of C_Lgreater than

10 pF is used.

10 pF

XIN XOUT

VDD GND

CTRL VDD

= 0W

Vin control

Clock output

GND

CLK

R1= 0 or 10

0.1uf

PLL501-01

0.1uf

Please order a test board without external C5 and C4 capacitors if you intend to use a crystal of CL equal to 10pF.

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 5/10/01 Page 1

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