TAS5760M
www.ti.com
SLOS772B –JULY 2013–REVISED JULY 2013
TSSOP PACKAGE
DAP-32
(TOP VIEW)
AVDD
SFT_CLIP
ANA_REG
VCOM
1
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
GVDD_REG
GGND
3
BSTRPA+
SPK_OUTA+
PVDD
4
ANA_REF
SPK_FAULT
SPK_SD
5
6
PGND
7
SPK_OUTA-
BSTRPA-
BSTRPB-
SPK_OUTB-
PGND
FREQ/SDA
8
PBTL/SCL
DVDD
9
10
11
12
13
14
15
16
SPK_GAIN0
SPK_GAIN1
SPK_SLEEP/ADR
MCLK
PowerPAD
PVDD
SPK_OUTB+
BSTRPB+
SCLK
DGND
LRCK
SDIN
Pin Descriptions
TAS5760M
Internal
Termination
No. Type(1)
Description
Name
AVDD
1
5
P
P
-
Power supply for internal analog circuitry
Connection point for internal reference used by ANA_REG and VCOM filter
capacitors
ANA_REF
-
Voltage regulator derived from AVDD supply (NOTE: This terminal is provided as a
connection point for filtering capacitors for this supply and must not be used to
power any external circuitry)
ANA_REG
3
P
-
Connection point for the SPK_OUTA- bootstrap capacitor, which is used to create a
power supply for the high-side gate drive for SPK_OUTA-
BSTRPA-
BSTRPA+
BSTRPB-
BSTRPB+
25
30
24
19
P
P
P
P
-
-
-
-
Connection point for the SPK_OUTA+ bootstrap capacitor, which is used to create a
power supply for the high-side gate drive for SPK_OUTA
Connection point for the SPK_OUTB- bootstrap capacitor, which is used to create a
power supply for the high-side gate drive for SPK_OUTB-
Connection point for the SPK_OUTB+ bootstrap capacitor, which is used to create a
power supply for the high-side gate drive for SPK_OUTB+
Ground for digital circuitry (NOTE: This terminal should be connected to the system
ground)
DGND
DVDD
18
10
8
G
P
-
-
Power supply for the internal digital circuitry
Weak Pull- Dual function terminal that functions as an I²C data input terminal in I²C Control
FREQ/SDA
DI
Down
Mode or as a Frequency Select terminal when in Hardware Control Mode.
Ground for gate drive circuitry (this terminal should be connected to the system
ground)
GGND
31
32
G
P
-
Voltage regulator derived from PVDD supply (NOTE: This terminal is provided as a
connection point for filtering capacitors for this supply and must not be used to
power any external circuitry)
GVDD_REG
-
Weak Pull- Word select clock for the digital signal that is active on the serial port's input data
Down line
LRCK
MCLK
17
14
DI
DI
Weak Pull- Master Clock used for internal clock tree, sub-circuit/state machine, and Serial Audio
Down
Port clocking
Dual function terminal that functions as an I²C clock input terminal in I²C Control
Mode or configures the device to operate in pre-filter Parallel Bridge Tied Load
(PBTL) mode when in Hardware Control Mode
Weak Pull-
Down
PBTL/SCL
9
DI
(1) AI = Analog input, AO = Analog output, DI = Digital Input, DO = Digital Output, P = Power, G = Ground (0V)
Copyright © 2013, Texas Instruments Incorporated
5
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