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TAS3108DCP PDF预览

TAS3108DCP

更新时间: 2024-01-01 17:04:14
品牌 Logo 应用领域
德州仪器 - TI 数字信号处理器
页数 文件大小 规格书
63页 1321K
描述
Digital Audio Processor 38-HTSSOP 0 to 70

TAS3108DCP 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:HTSSOP,针数:38
Reach Compliance Code:compliantHTS代码:8542.31.00.01
Factory Lead Time:6 weeks风险等级:5.61
地址总线宽度:桶式移位器:NO
边界扫描:NO最大时钟频率:20 MHz
外部数据总线宽度:格式:FIXED POINT
集成缓存:NO内部总线架构:MULTIPLE
JESD-30 代码:R-PDSO-G38JESD-609代码:e4
长度:9.7 mm低功率模式:YES
湿度敏感等级:3DMA 通道数量:
端子数量:38计时器数量:
最高工作温度:105 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:HTSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, HEAT SINK/SLUG, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260认证状态:Not Qualified
RAM(字数):3072座面最大高度:1.2 mm
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4.4 mm
uPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, OTHERBase Number Matches:1

TAS3108DCP 数据手册

 浏览型号TAS3108DCP的Datasheet PDF文件第4页浏览型号TAS3108DCP的Datasheet PDF文件第5页浏览型号TAS3108DCP的Datasheet PDF文件第6页浏览型号TAS3108DCP的Datasheet PDF文件第8页浏览型号TAS3108DCP的Datasheet PDF文件第9页浏览型号TAS3108DCP的Datasheet PDF文件第10页 
Not Recommended for New Designs  
TAS3108, TAS3108IA  
AUDIO DIGITAL SIGNAL PROCESSORS  
www.ti.com  
SLES152BOCTOBER 2005REVISED NOVEMBER 2007  
3.2 Terminal Descriptions  
TERMINAL  
NAME  
PULLUP/  
INPUT/  
PULLDOWN(2)  
DESCRIPTION  
OUTPUT(1)  
NO.  
38  
1
AVDD  
AVSS  
I
Analog power supply (3.3 V)  
Analog ground  
CS0  
7
I
I
Pulldown  
Chip select  
DVDD  
9, 30  
10, 29  
8
Digital power supply input (3.3 V)  
Digital ground  
DVSS  
GPIO  
I/O  
I/O  
I
Pullup  
GPIO control (user programmable)  
Sample rate clock (fS)  
LRCLK  
19  
5
Pulldown  
MCLKIN  
MCLKO  
MICROCLK_DIV  
Master clock input (connect to ground when not in use)  
Master clock output  
21  
6
O
I
Pulldown  
Pullup  
Internal microprocessor clock divide control  
Power down. Powers down all logic and stops all clocks, active low.  
Coefficient memory remains stable through the power-down cycle.  
PDN  
31  
I
PLL0  
PLL1  
34  
35  
36  
33, 37  
32  
16  
18  
20  
22  
23  
15  
17  
11  
12  
13  
14  
27  
26  
25  
24  
2
I
I
I
Pullup  
Pulldown  
Pullup  
PLL control 0  
PLL control 1  
PLL2  
PLL control 2  
RESERVED  
RESET  
SCL1  
Reserved. Connect to ground  
Reset, active low  
I2C port 1 clock (always a slave)  
I2C port 2 clock (always a master)  
Bit clock input  
I
I/O  
I/O  
I
Pullup  
SCL2  
SCLKIN  
SCLKOUT1  
SCLKOUT2  
SDA1  
Pulldown  
O
O
I/O  
I/O  
I
Bit clock 1 out. Used to receive input serial data.  
Bit clock 2 out. Used to clock output serial data.  
I2C port 1 data (always a slave)  
I2C port 2 data (always a master)  
Serial data input 1  
SDA2  
SDIN1  
Pulldown  
Pulldown  
Pulldown  
Pulldown  
SDIN2  
I
Serial data input 2  
SDIN3  
I
Serial data input 3  
SDIN4  
I
Serial data input 4  
SDOUT1  
SDOUT2  
SDOUT3  
SDOUT4  
VR_PLL  
XTALI  
O
O
O
O
Serial data output 1  
Serial data output 2  
Serial data output 3  
Serial data output 4  
Internal regulator. This pin must not be used to power external devices.  
Oscillator input (connect to ground when not in use)  
Oscillator output  
3
O
O
XTALO  
VR_DIG  
4
28  
Internal regulator. This pin must not be used to power external devices.  
(1) I = input, O = output  
(2) All pullups are 20-µA weak pullups, and all pulldowns are 20-µA weak pulldowns. The pullups and pulldowns are included to ensure  
proper input logic levels if the terminals are left unconnected (pullups logic 1 input; pulldowns logic 0 input). Devices that drive  
inputs with pullups must be able to sink 20 µA while maintaining a logic-0 drive level. Devices that drive inputs with pulldowns must be  
able to source 20 µA while maintaining a logic-1 drive level.  
3.3 Reset (RESET)  
The RESET pin is an asynchronous control signal that restores all TAS3108/TAS3108IA components to  
the default configuration. When a reset occurs, the audio DSP core is put into an idle state and the 8051  
starts initialization. A valid MCLKI or XTLI must be present when clearing the RESET pin to initiate a  
device reset. A reset can be initiated by applying a logic 0 on RESET. A reset can also be issued at power  
turnon by the three internal power supplies.  
Submit Documentation Feedback  
Physical Characteristics  
7

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