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TAS3108DCP PDF预览

TAS3108DCP

更新时间: 2024-02-10 13:42:52
品牌 Logo 应用领域
德州仪器 - TI 数字信号处理器
页数 文件大小 规格书
63页 1321K
描述
Digital Audio Processor 38-HTSSOP 0 to 70

TAS3108DCP 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:HTSSOP,针数:38
Reach Compliance Code:compliantHTS代码:8542.31.00.01
Factory Lead Time:6 weeks风险等级:5.61
地址总线宽度:桶式移位器:NO
边界扫描:NO最大时钟频率:20 MHz
外部数据总线宽度:格式:FIXED POINT
集成缓存:NO内部总线架构:MULTIPLE
JESD-30 代码:R-PDSO-G38JESD-609代码:e4
长度:9.7 mm低功率模式:YES
湿度敏感等级:3DMA 通道数量:
端子数量:38计时器数量:
最高工作温度:105 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:HTSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, HEAT SINK/SLUG, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260认证状态:Not Qualified
RAM(字数):3072座面最大高度:1.2 mm
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4.4 mm
uPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, OTHERBase Number Matches:1

TAS3108DCP 数据手册

 浏览型号TAS3108DCP的Datasheet PDF文件第1页浏览型号TAS3108DCP的Datasheet PDF文件第2页浏览型号TAS3108DCP的Datasheet PDF文件第3页浏览型号TAS3108DCP的Datasheet PDF文件第5页浏览型号TAS3108DCP的Datasheet PDF文件第6页浏览型号TAS3108DCP的Datasheet PDF文件第7页 
Not Recommended for New Designs  
TAS3108, TAS3108IA  
AUDIO DIGITAL SIGNAL PROCESSORS  
www.ti.com  
SLES152BOCTOBER 2005REVISED NOVEMBER 2007  
2.2 Power Supply  
The power supply contains supply regulators that provide analog and digital regulated power for various  
sections of the TAS3108/TAS3108IA. Only one external 3.3-V supply is required. All other voltages are  
generated on-chip from the external 3.3-V supply.  
2.3 Clock Control  
The TAS3108/TAS3108IA can be an audio data clock-master or clock-slave device. In clock-master mode,  
it generates MCLK, SCLK, and LRCLK. In clock-slave mode, it accepts MCLK, SCLK, and LRCLK. It can  
generate or accept master clocks from 6 MHz to 24.576 MHz. Master or slave operation is set via I2C  
register 0x00. The TAS3108/TAS3108IA can use a 6-MHz to 20-MHz crystal or a 6-MHz to 24.576-MHz,  
3.3-V MCLKI digital input as the master clock in either clock-master or clock-slave mode. In clock-slave  
mode, the master clock frequency does not need to be an integer multiple of the sample rate.  
The TAS3108/TAS3108IA does not support clock error detection. If a clock error occurs, the  
TAS3108/TAS3108IA does not prevent invalid data or clocks from being output. This means that the  
application system must be designed to handle clock errors.  
2.4 Serial Audio Ports (SAPs)  
Serial audio data is input via pins SDIN1, SDIN2, SDIN3, and SDIN4. Serial audio data is output on pins  
SDOUT1, SDOUT2, SDOUT3, and SDOUT4. The TAS3108/TAS3108IA accepts 32-, 44.1-, 48-, 88.2-,  
96-, 176.4-, or 192-kHz serial data as 16-, 20-, 24-, or 32-bit data in left justified, right justified, or I2S serial  
data formats. All four ports accommodate these three 2 channel data formats.  
In addition to supporting the 2 channel formats, SDIN1 and SDOUT1 also provide support for time-division  
multiplex (TDM) data formats of 4, 6, or 8 channels. The data formats are selectable via I2C register 0x00.  
All input channels must use the same data format. All output channels must use the same data format.  
However, the input and output formats can be different.  
2.5 M8051Warp Microprocessor  
The M8051Warp (8051) microprocessor controls I2C reads and writes and participates in some audio  
processing tasks requiring multiframe (fS period) processing cycles. The 8051 processor performs some  
control calculations and exchanges data between the audio DSP core and the I2C interface. It also  
provides mode control for the SAP interface and clock control. The microcode can program the GPIO pin  
for post-boot-up operation to be an input or an output. For more information, see the TAS3108/TAS3108IA  
Firmware Programmer's Guide (SLEU067).  
2.6 I2C Control Interface  
The TAS3108/TAS3108IA has an I2C slave-only interface (SDA1 and SCL1) for receiving commands and  
providing status to the system controller, and a separate master I2C interface (SDA2 and SCL2) to  
download programs and data from external memory such as an EEPROM. See Section 6 for more  
information.  
4
Functional Description  
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