Datasheet > T0504SP

T0504SP

更新时间： 2024-11-25 01:25:39

品牌	Logo	应用领域
竹懋 - CITC		/
页数	文件大小	规格书
8页	544K
描述
Ultra-Low Capacitance ESD Protection Device

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T0504SP 数据手册

T0504SP

Ultra-Low Capacitance ESD Protection Device

Chip Integration Technology Corporation

Features

Applications

□

Transient protection for high-speed data lines

IEC 61000-4-2 (ESD) ±25kV (Air)

±17kV (Contact)

IEC 61000-4-4 (EFT) 40A (5/50 ns)

Cable Discharge Event (CDE)

Package optimized for high-speed lines

Ultra-small package (2.5mmx1.0mmx0.55mm)

Protectssix data lines

Low capacitance: 0.2pF Typical(I/O-I/O)

Low leakage current: 0.1uA@V_RWM(Typical)

Low clamping voltage

Each I/O pin can withstand over 1000 ESD

strikes for ±8kV contact discharge

Serial ATA

PCI Express

Desktops, Servers and Notebooks

MDDI Ports

USB 2.0/3.0 Power and Data Line Protection

Display Ports

□

High Deﬁnition Multi-Media Interface (HDMI)

Digital Visual Interfaces (DVI)

Mechanical Characteristics

□

DFN2510-10L package

Flammability Rating: UL 94V-0

Marking: Part number

□

Packaging: Tape and Reel

Description

Circuit Diagram

T0504SP is an ultra-low capacitance Transient

Voltage Suppressor (TVS) designed to provide

electrostatic discharge (ESD) protection for high-

speed data interfaces. With typical capacitance of

0.2 pF only, T0504SP is designed to protect

I/O_4

I/O_2

parasitic-sensitive systems against over-voltage and

over-current transient events. It complies with IEC

61000-4-2 (ESD), Level 4 (±15kV air, ±8kV contact

discharge), IEC 61000-4-4 (electrical fast transien-t -

EFT) (40A,5/50 ns), very fast charged device model

(CDM) ESD and cable discharge event (CDE), etc.

GND

I/O_1

I/O_3

T0504SP uses ultra-small DFN2510-10L package.

Each T0504SP device can protect four high-speed

data lines The combined features of ultra-low

capacitance, ultra-small size and high ESD robustness

make T0504SP ideal for high-speed data ports and

high-frequency lines (e.g.,HDMI & DVI) application.s.

The low camping voltage of the T0504SP guarantees

a minimum stress on the protected IC.

Pin Conﬁguration

DFN2510-10L

(Top View)

Document ID : DS-22V15

Revised Date : 2017/07/20

Revision : C

12 3 4 5 6 7 8

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