Datasheet > SYS8512FKL-45

SYS8512FKL-45

更新时间： 2024-11-12 09:08:23

品牌	Logo	应用领域
MOSAIC		静态存储器光电二极管
页数	文件大小	规格书
7页	108K
描述
SRAM Module, 512KX8, 45ns, CMOS, PDIP32, PLASTIC, DIP-32

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SYS8512FKL-45 数据手册

Block Diagram

512K x 8 SRAM MODULE

SYS8512FK-20/25/35/45

11403 West Bernado Court, Suite 100, San Diego, CA 92127.

Tel No: (619) 674 2233, Fax No: (619) 674 2230

Issue 5.0 : November 1999

Description

Features

•

Access Times of 20/25/35/45 ns.

The SYS8512FK is plastic 4M Static RAM Module

housed in a standard 32 pin Dual-In-Line package

organised as 512K x 8. The module utilises fast

256Kx4 SRAMs housed in SOJ packages, and

uses double sided surface mount techniques to

achieve a very high density module.

32 Pin 0.6" Dual-In-Line package with

JEDEC compatible pinout.

•

5 Volt Supply ± 10%.

Low Power Dissipation:

Average (min cycle)

Standby -L (CMOS)

2.42W (maximum).

44mW (maximum).

The module has Chip Select, Write Enable and

Output Enable control inputs; the Output Enable

pinallowsfasteraccesstimesthanaddressaccess

during a Read Cycle.

•

Completely Static Operation.

Equal Access and Cycle Times.

All Inputs and Outputs Directly TTL Compatible

On-board Supply Decoupling Capacitors.

A0 - A17

D0 - D7

A18

A16

A14

A12

VCC

A15

A17

A13

256K X 4

SRAM

256K X 4

SRAM

256K X 4

SRAM

256K X 4

SRAM

A11

A10

DECODER

A18

Pin Functions

GND

Address Inputs

Data Input/Output

Chip Select

A0 - A18

D0 - D7

Package Details

Write Enable

Output Enable

Power (+5V)

Ground

Plastic 32 pin 0.6" Jedec DIP

V_CC

GND

12 3 4 5 6 7

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