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SYS8512FKXLI-70 PDF预览

SYS8512FKXLI-70

更新时间: 2024-11-11 03:14:15
品牌 Logo 应用领域
MOSAIC 静态存储器
页数 文件大小 规格书
7页 60K
描述
512K x 8 SRAM MODULE

SYS8512FKXLI-70 数据手册

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512K x 8 SRAM MODULE  
SYS8512FKX-70/85/10/12  
Issue 5.0: November 1999  
Features  
Description  
Access Times of 70/85/100/120 ns.  
TheSYS8512FKXisplastic4MStaticRAMModule  
housed in a standard 32 pin Dual-In-Line package  
organised as 512K x 8. The module utilises fast  
SRAMs housed in TSOP packages, and uses  
double sided surface mount techniques, buried  
decoder and dual board construction to achieve a  
very high density module.  
Lowseatedheight  
32 Pin 0.6" Dual-In-Line package with  
JEDEC compatible pinout.  
5 Volt Supply ± 10%.  
LowPowerDissipation:  
Average (min cycle)  
Standby(CMOS)  
605mW(maximum).  
44mW (maximum).  
The module has Chip Select, Write Enable and  
Output Enable control inputs; the Output Enable  
pinallowsfasteraccesstimesthanaddressaccess  
during a Read Cycle.  
Completely Static Operation.  
Equal Access and Cycle Times.  
All Inputs and Outputs Directly TTL Compatible.  
On-boardSupplyDecouplingCapacitors.  
Block Diagram  
Pin Definition  
AO - A 16  
D0 - D7  
A18  
A16  
A14  
A12  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
D0  
D1  
D2  
GND  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
1
2
3
4
5
6
7
8
VCC  
A15  
A17  
WE  
A13  
A8  
WE  
OE  
A9  
128K x 8  
SRAM  
128K x 8  
SRAM  
128K x 8  
SRAM  
CS  
128K x 8  
SRAM  
CS  
A11  
OE  
A10  
CS  
D7  
D6  
D5  
D4  
D3  
9
CS  
10  
11  
12  
13  
14  
15  
16  
CS  
DECODER  
Pin Functions  
A17  
A18  
Address Inputs  
A0 - A18  
D0 - D7  
CS  
CS  
Data Input/Output  
Chip Select Input  
Read/Write Input  
Output Enable Input  
Power (+5V)  
WE  
OE  
VCC  
Ground  
GND  

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