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SY10H606JZ-TR PDF预览

SY10H606JZ-TR

更新时间: 2024-09-30 21:06:51
品牌 Logo 应用领域
麦瑞 - MICREL /
页数 文件大小 规格书
5页 61K
描述
TTL/CMOS to PECL Translator, 6 Func, Complementary Output, PQCC28, LEAD FREE, PLASTIC, LCC-28

SY10H606JZ-TR 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:QCCJ,Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.75最大延迟:2.8 ns
接口集成电路类型:TTL/CMOS TO PECL TRANSLATORJESD-30 代码:S-PQCC-J28
JESD-609代码:e3长度:11.48 mm
湿度敏感等级:2位数:1
功能数量:6端子数量:28
最高工作温度:85 °C最低工作温度:
输出锁存器或寄存器:REGISTER输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:4.57 mm最大供电电压:5.25 V
最小供电电压:4.75 V标称供电电压:5 V
表面贴装:YES温度等级:COMMERCIAL EXTENDED
端子面层:Matte Tin (Sn)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:11.48 mm
Base Number Matches:1

SY10H606JZ-TR 数据手册

 浏览型号SY10H606JZ-TR的Datasheet PDF文件第2页浏览型号SY10H606JZ-TR的Datasheet PDF文件第3页浏览型号SY10H606JZ-TR的Datasheet PDF文件第4页浏览型号SY10H606JZ-TR的Datasheet PDF文件第5页 
6  
6  
REGISTERED HEX  
TTL-TO-PECL  
SY10H606  
SY100H606  
FEATURES  
DESCRIPTION  
Differential 50ECL outputs  
The SY10/100H606 are 6-bit, registered, single supply  
TTL-to-PECL translators. The devices feature differential  
PECL outputs as well as a choice between either a  
differential PECL clock input or a TTL clock input. The  
asynchronous master reset control is a PECL level input.  
With its differential ECL outputs and TTL inputs, the  
H606 device is ideally suited for the transmit function of  
a HPPI bus-type board-to-board interface application. The  
on-chip registers simplify the task of synchronizing the  
data between the two boards.  
Choice between differential PECL or TTL clock input  
Single +5V power supply  
VBB output for single-ended use  
Multiple power and ground pins to minimize noise  
Specified within-device skew  
Fully compatible with MC10H/100H606  
Available in 28-pin PLCC package  
The device is available in either ECL standard: the  
10H device is compatible with 10K logic levels, while the  
100H device is compatible with 100K logic levels.  
PIN NAMES  
BLOCK DIAGRAM  
Pin  
D0 – D5  
Function  
TTL Data Inputs  
CLK, CLK  
TCLK  
MR  
Differential PECL Clock Inputs  
TTL Clock Input  
1 OF 6 BITS  
Qn  
Qn  
PECL Master Reset Input  
True PECL Outputs  
Dn  
D
Q
Q0 – Q5  
Q0 – Q5  
VCCE  
Inverted PECL Outputs  
PECL VCC (5.0V)  
CLK  
VCCT  
TTL VCC (5.0V)  
R
GND  
TTL/PECL Ground  
VBB  
VBB Reference Output (PECL)  
CLK  
CLK  
TCLK  
MR  
VBB  
Rev.: E  
Amendment: /0  
M9999-032906  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: March 2006  

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