SY10H641AJCTR

更新时间： 2024-09-30 08:56:47

品牌	Logo	应用领域
麦瑞 - MICREL		逻辑集成电路驱动
页数	文件大小	规格书
5页	125K
描述
SINGLE SUPPLY 1:9 PECL-TO-TTL

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数据手册

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SY10H641AJCTR 数据手册

ClockWorks™

SY10H641A

ClockWorks™

SY100H641A

SY10H641A

SY100H641A

SINGLE SUPPLY 1:9

PECL-TO-TTL

SYNERGY

SEMICONDUCTOR

FEATURES

DESCRIPTION

■ Input frequencies up to 80MHz

■ PECL-to-TTL version of popular ECLinPS E111

■ Guaranteed low skew specification

■ Latched input

The SY10/100H641A are single supply, low skew

translating 1:9 clock drivers. Devices in the Synergy H600

translator series utilize the 28-lead PLCC for optimal

power pinning, signal flow-through and electrical

performance.

■ Differential ECL internal design

■ VBB output for single-ended operation

■ Single +5V supply

The devices feature a 24mA TTL output stage with

AC performance specified into a 50pF load capacitance.

A latch is provided on-chip. When LEN is LOW (or left

open, in which case it is pulled LOW by the internal pull-

downs), the latch is transparent. A HIGH on the enable

pin (EN) forces all outputs LOW.

■ Reset/enable

■ Extra TTL and ECL power/ground pins

The 10H version is compatible with MECL 10KH ECL

logic levels. The 100H version is compatible with 100K

levels.

■ Choice of ECL compatibility: MECL 10KH (10Hxxx)

or 100K (100Hxxx)

■ ESD protection of 2000V

■ Fully compatible with Motorola MC10H641/100H641

■ Available in 28-pin PLCC package

BLOCK DIAGRAM

PIN CONFIGURATION

TTL Outputs

24 23 22 21 20 19

TOP VIEW

PLCC

LEN

10 11

PECL Input

PIN NAMES

VBB

Function

LEN

TTL Ground (0V)

TTL VCC (+5.0V)

ECL VCC (+5.0V)

ECL Ground (0V)

Signal Input (PECL)

D, D

VBB

Q0 - Q8

VBB Reference Output (PECL)

Signal Outputs (TTL)

Enable Input (PECL)

LEN

Latch Enable Input (PECL)

Rev.: D

Amendment:/0

Issue Date: February, 1999

5-356

12 3 4 5

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