SY10EL15ZCTR

更新时间： 2024-01-11 21:34:36

品牌	Logo	应用领域
麦瑞 - MICREL		时钟
页数	文件大小	规格书
4页	65K
描述
1:4 CLOCK DISTRIBUTION

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中文翻译

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数据手册

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SY10EL15ZCTR 数据手册

Precision Edge™

SY10EL15

1:4 CLOCK

DISTRIBUTION

SY100EL15

FINAL

FEATURES

■ 50ps output-to-output skew

■ Synchronous enable/disable

■ Multiplexed clock input

Precision Edge™

DESCRIPTION

■ 75KΩ internal input pull-down resistors

■ Available in 16-pin SOIC package

The SY10/100EL15 are low skew 1:4 clock distribution

chips designed explicitly for low skew clock distribution

applications. The device can be driven by either a

differential or single-ended ECL or, if positive power

supplies are used, PECL input signal. If a single-ended

input is to be used the VBB output should be connected

to the CLK input and bypassed to VCC via a 0.01µF

capacitor. The VBB output is designed to act as the

switching reference for the input of the EL15 under single-

ended input conditions, as a result this pin can only

source/sink up to 0.5mA of current.

PIN CONFIGURATION/BLOCK DIAGRAM

CLK CLK

13 12

VBB

CC EN SCLK

VEE

SEL

16 15 14

The EL15 features a multiplexed clock input to allow

for the distribution of a lower speed scan or test clock

along with the high speed system clock. When LOW (or

left open and pulled LOW by the input pull-down resistor)

the SEL pin will select the differential clock input.

The common enable (EN) is synchronous so that the

outputs will only be enabled/disabled when they are

already in the LOW state. This avoids any chance of

generating a runt clock pulse when the device is enabled/

disabled as can happen with an asynchronous control.

The internal flip flop is clocked on the falling edge of the

input clock, therefore all associated specification limits

are referenced to the negative edge of the clock input.

SOIC

TOP VIEW

PIN NAMES

TRUTH TABLE

CLK

SCLK

Function

CLK

SCLK

SEL

Differential Clock Inputs

Synchronous Clock Input

Synchronous Enable

Clock Select Input

SEL

VBB

Reference Output

Q0-3

Differential Clock Outputs

* On next negative transition of CLK or SCLK

Precision Edge is a trademark of Micrel, Inc.

Rev.: G

Amendment:/0

Issue Date: February 2003

12 3 4

中文翻译

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