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SY10EL16VA

更新时间： 2024-01-12 01:56:26

品牌	Logo	应用领域
麦瑞 - MICREL		/
页数	文件大小	规格书
9页	161K
描述
ENHANCED DIFFERENTIAL RECEIVER

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SY10EL16VA 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	SOIC	包装说明：	SOP, SOP8,.25
针数：	8	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.09	Is Samacsys：	N
输入特性：	DIFFERENTIAL	接口集成电路类型：	LINE RECEIVER
接口标准：	GENERAL PURPOSE	JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e0	长度：	4.93 mm
湿度敏感等级：	1	标称负供电电压：	-3.3 V
功能数量：	1	端子数量：	8
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP8,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	峰值回流温度（摄氏度）：	240
电源：	-3.0/-5.5 V	认证状态：	Not Qualified
最大接收延迟：	0.325 ns	接收器位数：	1
座面最大高度：	1.73 mm	子类别：	Line Driver or Receivers
最大压摆率：	22 mA	表面贴装：	YES
技术：	BIPOLAR	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn85Pb15)	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	30	宽度：	3.94 mm
Base Number Matches：	1

SY10EL16VA 数据手册

ENHANCED

DIFFERENTIAL

RECEIVER

SY10EL16VA-VF

SY100EL16VA-VF

FEATURES

DESCRIPTION

■ 3.3V and 5V power supply options

■ 250ps propagation delay

The SY10/100EL16VA-VF are differential receivers.

The devices are equivalent to SY10/100EL16 or SY10/

100EL16V with enhanced capabilities. The QHG, /QHG

outputs have a DC gain several times larger than the DC

gain of the Q output.

The SY10/100EL16VA have an identical pinout to the

SY10/100EL16 or SY10/100EL16V. It provides a VBB

output for either single-ended application or as a DC

bias for AC coupling to the device.

■ Very high voltage gain vs. standard EL16 or EL16V

■ Ideal for Pulse Amplifier and Limiting Amplifier

applications

■ Data synchronous Enable/Disable (/EN) on QHG and

/QHG provides for complete glitchless gating of the

outputs

The SY10/100EL16VB are very similar to the SY10/

100EL16VA. The /Q output is provided for feedback

purposes.

■ Ideal for gating timing signals

■ Complete solution for high quality, high frequency

crystal oscillator applications

The SY10/100EL16VC provides an /EN input which is

synchronized with the data input (D) signal in a way that

providesglitchlessgatingoftheQHG and/QHG outputs. When

the /EN signal is LOW, the input is passed to the outputs and

the data output equals the data input. When the data input is

HIGH and the /EN goes HIGH, it will force the QHG LOW and

the /QHG HIGH on the next negative transition of the data

input. If the data input is LOW when the /EN goes HIGH, the

next data transition to a HIGH is ignored and QHG remains

LOW and /QHG remains HIGH. The next positive transition of

the data input is not passed on to the data outputs under these

conditions. The QHG and /QHG outputs remain in their dis-

abled state as long as the /EN input is held HIGH. The /EN

input has no influence on the /Q output and the data input is

passed on (inverted) to this output whether /EN is HIGH or

LOW. This configuration is ideal for crystal oscillator applica-

tions, where the oscillator can be free running and gated on

and off synchronously without adding extra counts to the

output.

■ Internal 75K Ohm input pull-down resistors

■ Available in both 8 and 16-pin SOIC package; 8 and

10-pin (3mm) MSOP and in DIE form

PIN NAMES

Function

Data Inputs

Data Outputs

QHG

VBB

/EN

Data Outputs w/High Gain

Reference Voltage Output

Enable Input

The SY10/100EL16VD provides the flexibility of all the

combinations in DIE form, in 16-pin 150mil SOIC package or

in 10-pin MSOP package. The 16-pin SOIC and 10-pin MSOP

packages are ideal for prototyping DIE applications.

TheSY10/100EL16VEaresimilar totheSY10/100EL16VB

where the Q, /Q output is made available differently. In this

package option, VBB is no longer provided.

TRUTH TABLE

/EN

QHG Output

Data

TheSY10/100EL16VFaresimilar totheSY10/100EL16VC,

offering the D, /D inputs rather than the VBB output.

Logic Low

Rev.: L

Amendment:/1

Issue Date: July 2000

12 3 4 5 6 7...9

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