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SY100EPT21LKI PDF预览

SY100EPT21LKI

更新时间: 2024-11-17 20:32:07
品牌 Logo 应用领域
美国微芯 - MICROCHIP 光电二极管接口集成电路锁存器
页数 文件大小 规格书
6页 110K
描述
PECL to TTL Translator, 1 Func, True Output, PDSO8, MSOP-8

SY100EPT21LKI 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:MSOP包装说明:TSSOP, TSSOP8,.19
针数:8Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.16Is Samacsys:N
最大延迟:2.5 ns接口集成电路类型:PECL TO TTL TRANSLATOR
JESD-30 代码:S-PDSO-G8JESD-609代码:e0
长度:3 mm湿度敏感等级:1
位数:1功能数量:1
端子数量:8最高工作温度:85 °C
最低工作温度:-40 °C输出锁存器或寄存器:NONE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP8,.19
封装形状:SQUARE封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):240电源:3.3 V
认证状态:Not Qualified座面最大高度:1.1 mm
子类别:Level Translators最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3 mm
Base Number Matches:1

SY100EPT21LKI 数据手册

 浏览型号SY100EPT21LKI的Datasheet PDF文件第2页浏览型号SY100EPT21LKI的Datasheet PDF文件第3页浏览型号SY100EPT21LKI的Datasheet PDF文件第4页浏览型号SY100EPT21LKI的Datasheet PDF文件第5页浏览型号SY100EPT21LKI的Datasheet PDF文件第6页 
3.3V DIFFERENTIAL  
LVPECL-to-LVTTL TRANSLATOR  
ECL Pro™  
SY100EPT21L  
FEATURES  
Guaranteed over the industrial temperature range:  
–40°C to +85°C  
Pin-for-pin; plug-in replacement to MC100EPT21D/DT  
3.3V power supply  
ECL Pro™  
DESCRIPTION  
1.9ns typical propagation delay  
275MHz f  
(Clock)  
MAX  
The SY100EPT21L is a single, differential LVPECL-  
to-LVTTL translator using a single +3.3V power supply.  
Because low voltage positive ECL (LVPECL) levels are  
used, only +3.3V and ground are required. The small  
outline 8-pin SOIC package and low-skew, single-gate  
design make the EPT21L ideal for applications that  
require the translation of a clock or data signal where  
minimal space, low power, and low cost are critical.  
Differential LVPECL inputs  
24mA LVTTL output  
Flow-through pinout  
Q output will default LOW with inputs open  
V output  
BB  
Available in 8-pin MSOP and SOIC packages  
V
allows a differential, single-ended, or AC-coupled  
BB  
interface to the device. If used, the V output should be  
BB  
bypassed to V  
with 0.01µF capacitor.  
CC  
Under open input conditions, the /D will be biased at a  
/2 voltage level and the D input will be pulled to  
V
CC  
ground. This condition will force the Q output low to  
provide added stability.  
APPLICATIONS  
The 100EPT is compatible with positive ECL 100K  
logic levels. For applications that require the smallest  
footprint, consider the SY89321L in an ultra-small  
(2mm × 2mm) 8-pin MLF™ package.  
All support documentation can be found on Micrel’s web  
site at: www.micrel.com.  
ASIC/FPGA interface  
Legacy interface  
Precision differential-to-general purpose, single-  
ended translation  
CROSS REFERENCE TABLE  
Micrel  
ON Semiconductor  
MC100EPT21D  
SY100EPT21LZI  
SY100EPT21LZITR  
SY100EPT21LKI  
SY100EPT21LKITR  
MC100EPT21DR2  
MC100EPT21DT  
MC100EPT21DTR2  
ECL Pro is a trademark of Micrel, Inc.  
MicroLeadFrame and MLF are trademarks of Amkor Technology, Inc.  
Rev.: E  
Amendment: /0  
M9999-120505  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: December2005  

SY100EPT21LKI 替代型号

型号 品牌 替代类型 描述 数据表
SY100EPT21LZG MICROCHIP

完全替代

PECL TO TTL TRANSLATOR, TRUE OUTPUT, PDSO8
SY100EPT21LKG MICROCHIP

完全替代

PECL TO TTL TRANSLATOR, TRUE OUTPUT, PDSO8

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