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STM8AF5268UBU PDF预览

STM8AF5268UBU

更新时间: 2024-12-01 05:52:03
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 外围集成电路
页数 文件大小 规格书
114页 1430K
描述
MICROCONTROLLER

STM8AF5268UBU 技术参数

生命周期:Active包装说明:HVQCCN,
Reach Compliance Code:compliant风险等级:5.84
位大小:8端子数量:48
封装代码:HVQCCN技术:CMOS
uPs/uCs/外围集成电路类型:MICROCONTROLLER

STM8AF5268UBU 数据手册

 浏览型号STM8AF5268UBU的Datasheet PDF文件第2页浏览型号STM8AF5268UBU的Datasheet PDF文件第3页浏览型号STM8AF5268UBU的Datasheet PDF文件第4页浏览型号STM8AF5268UBU的Datasheet PDF文件第5页浏览型号STM8AF5268UBU的Datasheet PDF文件第6页浏览型号STM8AF5268UBU的Datasheet PDF文件第7页 
STM8AF5xxx  
STM8AF6x69/7x/8x/9x/Ax  
Automotive 8-bit MCU, with up to 128 Kbytes Flash, data EEPROM,  
10-bit ADC, timers, LIN, CAN, USART, SPI, I2C, 3 to 5.5 V  
Datasheet - production data  
Features  
Core  
– Max f  
: 24 MHz  
CPU  
LQFP48 7x7  
LQFP64 10x10  
LQFP80 14x14  
– Advanced STM8A core with Harvard  
architecture and 3-stage pipeline  
– Average 1.6 cycles/instruction resulting in  
10 MIPS at 16 MHz f  
standard benchmark  
for industry  
CPU  
LQFP32 7x7  
VFQFPN32 5x5  
Communication interfaces  
Memories  
– High speed 1 Mbit/s CAN 2.0B interface  
– USART with clock output for synchronous  
operation - LIN master mode  
– Program memory: 32 to 128 Kbytes Flash  
program; data retention 20 years at 55 °C  
– Data memory: up to 2 Kbytes true data  
EEPROM; endurance 300 kcycles  
– LINUART LIN 2.2 compliant, master/slave  
modes with automatic resynchronization  
– SPI interface up to 10 Mbit/s or f  
– RAM: 2 Kbytes to 6 Kbytes  
/2  
MASTER  
2
Clock management  
– I C interface up to 400 Kbit/s  
– Low-power crystal resonator oscillator with  
external clock input  
– Internal, user-trimmable 16 MHz RC and  
low-power 128 kHz RC oscillators  
– Clock security system with clock monitor  
Analog to digital converter (ADC)  
– 10-bit resolution, 2 LSB TUE, 1 LSB  
linearity and up to 16 multiplexed channels  
Operating temperature up to 150 °C  
Qualification conforms to AEC-Q100 grade 0  
Reset and supply management  
– Wait/auto-wakeup/Halt low-power modes  
with user definable clock gating  
– Low consumption power-on and power-  
down reset  
(1)  
Table 1. Device summary  
Reference  
Part number  
STM8AF5169, STM8AF5189,  
STM8AF5198  
(2)  
STM8AF51xx (with CAN)  
Interrupt management  
STM8AF5268, STM8AF5269,  
STM8AF5286, STM8AF5288,  
STM8AF5289, STM8AF528A,  
STM8AF52A8, STM8AF52A9,  
STM8AF52AA, STM8AF52A6  
– Nested interrupt controller with 32 vectors  
– Up to 37 external interrupts on 5 vectors  
STM8AF52xx (with CAN)  
Timers  
– 2 general purpose 16-bit timers with up to 3  
CAPCOM channels each (IC, OC, PWM)  
– Advanced control timer: 16-bit, 4 CAPCOM  
channels, 3 complementary outputs, dead-  
time insertion and flexible synchronization  
– 8-bit AR basic timer with 8-bit prescaler  
– Auto-wakeup timer  
STM8AF6178, STM8AF6199,  
STM8AF619A  
(2)  
STM8AF61xx  
STM8AF6269, STM8AF6286,  
STM8AF6288, STM8AF6289,  
STM8AF628A, STM8AF62A6,  
STM8AF62A8, STM8AF62A9,  
STM8AF62AA  
STM8AF62xx  
1. In the order code, ‘F’ applies to devices with Flash program  
memory and data EEPROM while ‘H’ refers to devices with  
Flash program memory only. ‘F’ is replaced by ‘P’ for devices  
with FASTROM (see Tables 2, 3, 4, and 5, and Figure 53).  
– Window and independent watchdog timers  
I/Os  
– Up to 68 user pins (11 high sink I/Os)  
– Highly robust I/O design, immune against  
current injection  
2. Not recommended for new design.  
June 2014  
DocID14395 Rev 11  
1/114  
This is information on a product in full production.  
www.st.com  
 
 
 
 
 
 
 
 
 
 

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