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STK10C48-N25I PDF预览

STK10C48-N25I

更新时间: 2024-02-17 11:11:24
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
12页 396K
描述
2KX8 NON-VOLATILE SRAM, 25ns, PDSO28, 0.300 INCH, PLASTIC, SOIC-28

STK10C48-N25I 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:SOP, SOP28,.4Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.41
风险等级:5.53最长访问时间:25 ns
其他特性:HARDWARE STORE/RECALL; AUTOMATIC STORE TIMINGJESD-30 代码:R-PDSO-G28
JESD-609代码:e0长度:17.935 mm
内存密度:16384 bit内存集成电路类型:NON-VOLATILE SRAM
内存宽度:8功能数量:1
端子数量:28字数:2048 words
字数代码:2000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:2KX8封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP28,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
并行/串行:PARALLEL电源:5 V
认证状态:Not Qualified座面最大高度:2.64 mm
最大待机电流:0.00075 A子类别:SRAMs
最大压摆率:0.085 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:7.505 mm
Base Number Matches:1

STK10C48-N25I 数据手册

 浏览型号STK10C48-N25I的Datasheet PDF文件第1页浏览型号STK10C48-N25I的Datasheet PDF文件第2页浏览型号STK10C48-N25I的Datasheet PDF文件第4页浏览型号STK10C48-N25I的Datasheet PDF文件第5页浏览型号STK10C48-N25I的Datasheet PDF文件第6页浏览型号STK10C48-N25I的Datasheet PDF文件第7页 
STK10C48  
SRAM READ CYCLES #1 & #2  
(V = 5.0V 10%)  
CC  
SYMBOLS  
NO.  
STK10C48-25 STK10C48-35 STK10C48-45  
PARAMETER  
UNITS  
#1, #2  
Alt.  
MIN  
MAX  
MIN  
MAX  
MIN  
MAX  
1
2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Chip Enable Access Time  
25  
35  
45  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ELQV  
ACS  
f
Read Cycle Time  
25  
35  
45  
AVAV  
RC  
AA  
g
3
Address Access Time  
25  
10  
35  
15  
45  
20  
AVQV  
4
Output Enable to Data Valid  
Output Hold after Address Change  
Chip Enable to Output Active  
Chip Disable to Output Inactive  
Output Enable to Output Active  
Output Disable to Output Inactive  
Chip Enable to Power Active  
Chip Disable to Power Standby  
GLQV  
OE  
OH  
LZ  
g
5
5
5
5
5
5
5
AXQX  
6
ELQX  
h
7
10  
10  
25  
13  
13  
35  
15  
15  
45  
EHQZ  
HZ  
8
0
0
0
0
0
0
GLQX  
OLZ  
OHZ  
PA  
h
9
GHQZ  
e
10  
11  
ELICCH  
EHICCL  
d, e  
PS  
Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles. NE must be high during entire cycle.  
Note g: I/O state assumes E, G < VIL, W > VIH , and NE VIH; device is continuously selected.  
Note h: Measured + 200mV from steady state output voltage.  
f, g  
SRAM READ CYCLE #1: Address Controlled  
2
t
AVAV  
ADDRESS  
3
t
AVQV  
5
t
AXQX  
DQ (DATA OUT)  
DATA VALID  
f
SRAM READ CYCLE #2: E Controlled  
2
t
AVAV  
ADDRESS  
E
1
11  
EHICCL  
t
ELQV  
t
6
t
ELQX  
7
t
EHQZ  
G
9
t
4
GHQZ  
t
GLQV  
8
t
GLQX  
DQ (DATA OUT)  
DATA VALID  
10  
ELICCH  
t
ACTIVE  
STANDBY  
I
CC  
March 2006  
3
Document Control # ML0002 rev 0.2  

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