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STE2001

更新时间: 2024-02-03 05:50:58
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 驱动程序和接口接口集成电路控制器
页数 文件大小 规格书
36页 314K
描述
65 X 128 SINGLE CHIP LCD CONTROLLER / DRIVER

STE2001 技术参数

生命周期:ObsoleteReach Compliance Code:compliant
风险等级:5.84Is Samacsys:N
显示模式:SEGMENT底板数:65-BP
区段数:128最高工作温度:85 °C
最低工作温度:-40 °C封装等效代码:DIE OR CHIP
电源:2/5 V认证状态:Not Qualified
子类别:Other Interface ICs最大压摆率:0.35 mA
技术:CMOS温度等级:INDUSTRIAL
Base Number Matches:1

STE2001 数据手册

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STE2001  
65 X 128 SINGLE CHIP LCD CONTROLLER / DRIVER  
PRODUCT PREVIEW  
65 x 128 bits Display Data RAM  
Low Power Consumption, suitable for battery  
operated systems  
Configurable matrix: 65 x 128 or 33 x 128  
Programmable (65/33) MUX rate  
Row by Row Scrolling  
Logic Supply Voltage range from 1.9 to 5V  
High Voltage Generator Supply Voltage range  
from 2.4 to 4.5V  
Automatic data RAM Blanking procedure  
Display Supply Voltage range from 4.5 to 9V  
Selectable Input Interface:  
2
I C Bus Fast and Hs-mode (read and write)  
DESCRIPTION  
Parallel Interface (write only)  
Serial Interface (write only)  
The STE2001 is a low power CMOS LCD controller  
driver. Designed to drive a 65 rows by 128 columns  
graphic display, provides all necessary functions in a  
single chip, including on-chip LCD supply and bias  
voltages generators, resulting in a minimum of exter-  
nals components and in a very low power consump-  
tion. The STE2001 features three standard interfaces  
Fully Integrated Oscillator requires no external  
components  
Fully Integrated Configurable LCD bias voltages  
generator with:  
Selectable (5X, 4X, 3X, 2X) multiplication factor  
Effective sensing for High Precision Output  
Four selectable temperature compensation  
coefficients  
2
(Serial, parallel, I C) for ease of interfacing with the  
host µcontroller.  
Type  
Bumped Wafers  
BumpedDice on Waffle Pack  
Ordering Number  
STE2001DIE1  
Designed for chip-on-glass (COG) applications  
Programmable bottom row pads mirroring and  
top row pads mirroring for compatible with both  
TCP and COG applications  
STE2001DIE2  
Figure 1. Block Diagram  
CO to C127  
R0 to R64  
TIMING  
GENERATOR  
COLUMN  
DRIVERS  
ROW  
DRIVERS  
OSC  
OSC  
CLOCK  
BIAS VOLTAGE  
GENERATOR  
VLCDIN  
DATA  
SHIFT  
LATCHES  
REGISTER  
VLCDSENSE  
VLCDOUT  
HIGH VOLTAGE  
GENERATOR  
65 x 128  
RAM  
SCROLL  
LOGIC  
RES  
RESET  
TEST_0_13  
BSY_FLG  
VDD1,2,3  
TEST  
DISPLAY  
CONTROL  
LOGIC  
DATA  
REGISTER  
INSTRUCTION  
REGISTER  
V
SS1,2  
SEL1,2  
2
I CBUS  
PARALLEL  
SERIAL  
D00IN1137  
SAO SCL  
SDA_IN SDA_OUT DB0 to DB7 E  
PD/C SCE SDIN SCLK SD/C  
October 2001  
1/36  
This is preliminary information on a new product now in development. Details are subject to change without notice.  

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