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ST8500

更新时间： 2023-12-20 18:45:40

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ST8500 数据手册

ST8500

Device architecture

The ST8500 architecture is composed of the following parts:

1. PLC front-end including digital front-end (DFE) and analog front-end (AFE)

2. Real-time engine: the digital core running the lower layers of the PLC protocol stack

and implementing modulation, demodulation and advanced forward error corrections

(FEC) algorithms

3. Protocol engine: the digital core running the upper layers of the PLC protocol stack and

managing the interface with external microcontrollers.

4. Peripherals, crypto, debug section

5. Clock and reset section

6. Power management section

The ST8500 detailed architecture is shown in Figure 2.

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