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ST52T520F2B1 PDF预览

ST52T520F2B1

更新时间: 2023-07-15 00:00:00
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
94页 575K
描述
ST52T520F2B1

ST52T520F2B1 数据手册

 浏览型号ST52T520F2B1的Datasheet PDF文件第2页浏览型号ST52T520F2B1的Datasheet PDF文件第3页浏览型号ST52T520F2B1的Datasheet PDF文件第4页浏览型号ST52T520F2B1的Datasheet PDF文件第5页浏览型号ST52T520F2B1的Datasheet PDF文件第6页浏览型号ST52T520F2B1的Datasheet PDF文件第7页 
ST52F500/F503/F504  
ST52F500/F503/F504  
8-BIT INTELLIGENT CONTROLLER UNIT (ICU)  
2
Two Timer/PWMs, I C, SPI  
TARGET SPECIFICATION  
Memories  
Up to 8 Kbytes Single Voltage Flash Memory  
Up to 512 bytes of RAM  
Up to 4 Kbytes Data EEPROM  
In Situ Programming in Flash devices (ISP)  
Single byte and Page modes and In Application  
Programming for writing data in Flash memory  
Readout protection and flexible write protection  
Core  
Register File based architecture  
107 basic instructions  
Hardware multiplication and division  
Decision Processor for the implementation of  
Fuzzy Logic algorithms  
Deep System and User Stacks  
Clock and Power Supply  
Up to 24 MHz clock frequency  
Programmable Oscillator modes:  
Peripherals  
2 Programmable 16 bit Timer/PWMs with  
internal 16-bit Prescaler featuring:  
– 10 MHz Internal Oscillator  
– External Clock/ Oscillator  
– External RC Oscillator  
Power-On Reset (POR)  
– PWM output  
– Input capture  
Programmable Low Voltage Detector (PLVD)  
– Output compare  
– Pulse generator mode  
Watchdog timer  
with 3 configurable thresholds  
Power Saving features  
2
I C Peripheral with master and slave mode  
Interrupts  
3-wire SPI Peripheral supporting Single  
8 interrupt vectors with one SW Trap  
Non-Maskable Interrupt (NMI)  
Master and Multi Master SPI modes  
Two Port Interrupts with up to 16 sources  
Development tools  
High level Software tools  
‘C’ Compiler  
I/O Ports  
From 10 up to 22 I/O PINs configurable in pull-  
up, push-pull, weak pull-up, open-drain and  
high-impedance  
Emulator  
Low cost Programmer  
Gang Programmer  
High current sink/source in all pins  
Rev 1.1 - January 2002  
1/94  
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.  

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