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SST5546NL-T1

更新时间： 2024-11-26 21:01:43
品牌 Logo 应用领域
威世 - VISHAY 开关光电二极管晶体管
页数 文件大小 规格书
6页 79K
描述
Small Signal Field-Effect Transistor, 2-Element, N-Channel, Silicon, Junction FET, SOIC-8

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SST5546NL-T1 技术参数

生命周期：Obsolete零件包装代码：SOT
包装说明：SMALL OUTLINE, R-PDSO-G8针数：8
Reach Compliance Code：unknown风险等级：5.84
其他特性：LOW NOISE配置：SEPARATE, 2 ELEMENTS
FET 技术：JUNCTION最大反馈电容 (Crss)：2 pF
JESD-30 代码：R-PDSO-G8元件数量：2
端子数量：8工作模式：DEPLETION MODE
封装主体材料：PLASTIC/EPOXY封装形状：RECTANGULAR
封装形式：SMALL OUTLINE极性/信道类型：N-CHANNEL
认证状态：Not Qualified表面贴装：YES
端子形式：GULL WING端子位置：DUAL
晶体管应用：SWITCHING晶体管元件材料：SILICON
Base Number Matches：1

SST5546NL-T1 数据手册

 浏览型号SST5546NL-T1的Datasheet PDF文件第2页浏览型号SST5546NL-T1的Datasheet PDF文件第3页浏览型号SST5546NL-T1的Datasheet PDF文件第4页浏览型号SST5546NL-T1的Datasheet PDF文件第5页浏览型号SST5546NL-T1的Datasheet PDF文件第6页 
SST/U5545NL Series  
New Product  
Vishay Siliconix  
Monolithic N-Channel JFET Duals  
PRODUCT SUMMARY  
Part Number  
VGS(off) (V)  
V(BR)GSS Min (V) gfs Min (mS) IG Max (pA) jVGS1 - VGS2j Max (mV)  
U5545NL  
-0.5 to -4.5  
-0.5 to -4.5  
-0.5 to -4.5  
-50  
-50  
-50  
1.5  
1.5  
1.5  
-50  
-50  
-50  
5
SST/U5546NL  
SST/U5547NL  
10  
15  
FEATURES  
BENEFITS  
APPLICATIONS  
D Anti Latchup Capability  
D Monolithic Design  
D High Slew Rate  
D External Substrate Bias—Avoids Latchup  
D Wideband Differential Amps  
D Tight Differential Match vs. Current  
D High-Speed, Temp-Compensated,  
Single-Ended Input Amps  
D Improved Op Amp Speed, Settling Time  
Accuracy  
D High-Speed Comparators  
D Low Offset/Drift Voltage  
D Low Gate Leakage: 3 pA  
D Low Noise  
D Minimum Input Error/Trimming Requirement  
D Insignificant Signal Loss/Error Voltage  
D High System Sensitivity  
D Impedance Converters  
D High CMRR: 100 dB  
D Minimum Error with Large Input Signal  
DESCRIPTION  
The SST/U5545NL Series are monolithic dual n-channel  
JFETs designed to provide high input impedance (IG < 50 pA)  
for general purpose differential amplifiers. The U5545NL  
features minimum system error and calibration (5-mV offset  
maximum).  
The SST5546NL/47NL in the SO-8 package provide ease of  
manufacturing. The symmetrical pinout prevents improper  
orientation.  
These part number are available with  
tape-and-reel options for compatibility with automatic  
assembly methods.  
Pins 4 and 8 on the SST series and pin 4 on the U series part  
numbers enable the substrate to be connected to a positive,  
external bias (VDD) to avoid latchup.  
The hermetically sealed TO-78 package is available with full  
military processing.  
TO-78  
S
G
2
1
Narrow Body SOIC  
1
3
7
5
S
D
G
SUBSTRATE  
1
2
3
4
8
7
6
5
1
1
1
D
1
D
2
G
2
2
6
D
2
SUBSTRATE  
S
2
G
1
S
2
4
Top View  
CASE, SUBSTRATE  
Top View  
U5545NL  
U5546NL  
U5547NL  
Marking Codes:  
SST5546NL - (5546NL)  
SST5547NL - (5547NL)  
ABSOLUTE MAXIMUM RATINGS  
a
Gate-Drain, Gate-Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 V  
Gate Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA  
Power Dissipation :  
Notes  
Per Side . . . . . . . . . . . . . . . . . . . . . . . . 250 mW  
b
Total . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW  
1
Lead Temperature ( / ” from case for 10 sec.) . . . . . . . . . . . . . . . . . . . 300_C  
16  
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 200_C  
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -55 to 150_C  
a. Derate 2 mW/_C above 25_C  
b. Derate 4 mW/_C above 25_C  
Document Number: 72119  
S-03162—Rev. A, 14-Feb-03  
www.vishay.com  
7-1  
123456

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