16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory
SST34HF1681
SST34HF16818 Mb Flash (x16) Concurrent SuperFlash ComboMemory
Advance Specifications
FEATURES:
•
•
Flash Organization: 1M x16
Dual-Bank Architecture for Concurrent
Read/Write Operation
•
•
Block-Erase Capability
– Uniform 32 KWord blocks
Read Access Time
– 16 Mbit: 12 Mbit + 4 Mbit
SRAM Organization:
– Flash: 70 and 90 ns
– SRAM: 70 and 90 ns
•
– 8 Mbit: 512K x16
•
•
Latched Address and Data
Fast Erase and Word-Program:
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Word-Program Time: 14 µs (typical)
– Chip Rewrite Time: 8 seconds (typical)
•
•
Single 2.7-3.3V Read and Write Operations
Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
•
•
Low Power Consumption:
– Active Current: 25 mA (typical)
– Standby Current: 20 µA (typical)
•
•
Automatic Write Timing
– Internal VPP Generation
End-of-Write Detection
– Toggle Bit
– Data# Polling
– Ready/Busy# pin
Hardware Sector Protection (WP#)
– Protects 4 outer most sectors (4 KWord) in the
larger bank by holding WP# low and unprotects
by holding WP# high
Hardware Reset Pin (RST#)
– Resets the internal state machine to reading
data array
•
•
•
•
•
CMOS I/O Compatibility
JEDEC Standard Command Set
Conforms to Common Flash Memory Interface
(CFI)
Packages Available
Sector-Erase Capability
– Uniform 1 KWord sectors
•
– 56-ball LFBGA (8mm x 10mm)
PRODUCT DESCRIPTION
The SST34HF1681 ComboMemory devices integrate a
1M x16 CMOS flash memory bank with a 512K x16 CMOS
SRAM memory bank in a Multi-Chip Package (MCP).
These devices are fabricated using SST’s proprietary, high-
performance CMOS SuperFlash technology incorporating
the split-gate cell design and thick oxide tunneling injector
to attain better reliability and manufacturability compared
with alternate approaches. The SST34HF1681 devices are
ideal for applications such as cellular phones, GPSs, PDAs
and other portable electronic devices in a low power and
small form factor system.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore, the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles. The SST34HF1681 devices offer a guaran-
teed endurance of 10,000 cycles. Data retention is rated at
greater than 100 years. With high performance Word-Pro-
gram, the flash memory banks provide a typical Word-Pro-
gram time of 14 µsec. The entire flash memory bank can
be erased and programmed word-by-word in typically 8
seconds for the SST34HF1681, when using interface fea-
tures such as Toggle Bit or Data# Polling to indicate the
completion of Program operation. To protect against inad-
vertent flash write, the SST34HF1681 devices contain on-
chip hardware and software data protection schemes.
The SST34HF1681 features dual flash memory bank
architecture allowing for concurrent operations between the
two flash memory banks and the SRAM. The devices can
read data from either bank while an Erase or Program
operation is in progress in the opposite bank. The two flash
memory banks are partitioned into 4 Mbit and 12 Mbit with
top or bottom sector protection options for storing boot
code, program code, configuration/parameter data and
user data.
The flash and SRAM operate as two independent memory
banks with respective bank enable signals. The memory
bank selection is done by two bank enable signals. The
©2001 Silicon Storage Technology, Inc.
SST, the SST logo, and SuperFlash are Trademarks registered by Silicon Storage Technology, Inc. in the U.S. Patent and Trademark Office.
Concurrent SuperFlash, CSF, and ComboMemory are trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
S71214-00-000 12/01
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