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SST31LF021-70-4E-WH PDF预览

SST31LF021-70-4E-WH

更新时间： 2024-02-17 10:07:59
品牌 Logo 应用领域
SST 闪存内存集成电路静态存储器光电二极管
页数 文件大小 规格书
24页 293K
描述
2 Mbit Flash + 1 Mbit SRAM ComboMemory

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SST31LF021-70-4E-WH 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：TSOP1包装说明：TSOP1, TSSOP32,.56,20
针数：32Reach Compliance Code：unknown
HTS代码：8542.32.00.71风险等级：5.92
Is Samacsys：N最长访问时间：70 ns
其他特性：STATIC RAM IS ORGANIZED AS 128K X 8JESD-30 代码：R-PDSO-G32
长度：12.4 mm内存密度：2097152 bit
内存集成电路类型：MEMORY CIRCUIT内存宽度：8
混合内存类型：FLASH+SRAM功能数量：1
端子数量：32字数：262144 words
字数代码：256000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-20 °C
组织：256KX8封装主体材料：PLASTIC/EPOXY
封装代码：TSOP1封装等效代码：TSSOP32,.56,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3.3 V
认证状态：Not Qualified座面最大高度：1.2 mm
最大待机电流：0.00003 A子类别：Other Memory ICs
最大压摆率：0.055 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL EXTENDED端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：8 mm
Base Number Matches：1

SST31LF021-70-4E-WH 数据手册

 浏览型号SST31LF021-70-4E-WH的Datasheet PDF文件第2页浏览型号SST31LF021-70-4E-WH的Datasheet PDF文件第3页浏览型号SST31LF021-70-4E-WH的Datasheet PDF文件第4页浏览型号SST31LF021-70-4E-WH的Datasheet PDF文件第5页浏览型号SST31LF021-70-4E-WH的Datasheet PDF文件第6页浏览型号SST31LF021-70-4E-WH的Datasheet PDF文件第7页 
2 Mbit Flash + 1 Mbit SRAM ComboMemory  
SST31LF021 / SST31LF021E  
SST31LF021 / 021E2 Mb Flash (x8) + 1 Mb SRAM (x8) Monolithic ComboMemories  
Data Sheet  
FEATURES:  
•
Monolithic Flash + SRAM ComboMemory  
– SST31LF021/021E: 256K x8 Flash + 128K x8 SRAM  
Single 3.0-3.6V Read and Write Operations  
Concurrent Operation  
•
•
Fast Read Access Times:  
– SST31LF021  
Flash: 70 ns  
SRAM: 70 ns  
Flash: 300 ns  
SRAM: 300 ns  
•
•
– SST31LF021E  
– Read from or Write to SRAM while  
Erase/Program Flash  
Flash Fast Erase and Byte-Program:  
– Sector-Erase Time: 18 ms (typical)  
– Bank-Erase Time: 70 ms (typical)  
– Byte-Program Time: 14 µs (typical)  
– Bank Rewrite Time: 4 seconds (typical)  
Flash Automatic Erase and Program Timing  
– Internal VPP Generation  
•
•
Superior Reliability  
– Endurance: 100,000 Cycles (typical)  
– Greater than 100 years Data Retention  
Low Power Consumption:  
•
•
– Active Current: 10 mA (typical) for Flash and  
20 mA (typical) for SRAM Read  
– Standby Current: 10 µA (typical)  
Flash End-of-Write Detection  
– Toggle Bit  
– Data# Polling  
•
•
Flash Sector-Erase Capability  
– Uniform 4 KByte sectors  
•
•
•
CMOS I/O Compatibility  
JEDEC Standard Command Set  
Package Available  
Latched Address and Data for Flash  
– 32-lead TSOP (8mm x 14mm)  
PRODUCT DESCRIPTION  
The SST31LF021/021E devices are a 256K x8 CMOS  
flash memory bank combined with a 128K x8 or 32K x8  
CMOS SRAM memory bank manufactured with SST’s  
proprietary, high performance SuperFlash technology. Two  
pinout standards are available for these devices. The  
SST31LF021 conform to JEDEC standard flash pinouts  
and the SST31LF021E conforms to standard EPROM  
pinouts. The SST31LF021/021E devices write (SRAM or  
flash) with a 3.0-3.6V power supply. The monolithic  
SST31LF021/021E devices conform to Software Data  
Protect (SDP) commands for x8 EEPROMs.  
The SST31LF021/021E operate as two independent mem-  
ory banks with respective bank enable signals. The SRAM  
and flash memory banks are superimposed in the same  
memory address space. Both memory banks share com-  
mon address lines, data lines, WE# and OE#. The memory  
bank selection is done by memory bank enable signals.  
The SRAM bank enable signal, BES# selects the SRAM  
bank and the flash memory bank enable signal, BEF#  
selects the flash memory bank. The WE# signal has to be  
used with Software Data Protection (SDP) command  
sequence when controlling the Erase and Program opera-  
tions in the flash memory bank. The SDP command  
sequence protects the data stored in the flash memory  
bank from accidental alteration.  
Featuring high performance Byte-Program, the flash  
memory bank provides a maximum Byte-Program time of  
20 µsec. The entire flash memory bank can be erased and  
programmed byte-by-byte in typically 4 seconds, when  
using interface features such as Toggle Bit or Data# Poll-  
ing to indicate the completion of Program operation. To  
protect against inadvertent flash write, the SST31LF021/  
021E devices have on-chip hardware and Software Data  
Protection schemes. Designed, manufactured, and tested  
for a wide spectrum of applications, the SST31LF021/  
021E devices are offered with a guaranteed endurance of  
10,000 cycles. Data retention is rated at greater than 100  
years.  
The SST31LF021/021E provide the added functionality of  
being able to simultaneously read from or write to the  
SRAM bank while erasing or programming in the flash  
memory bank. The SRAM memory bank can be read or  
written while the flash memory bank performs Sector-  
Erase, Bank-Erase, or Byte-Program concurrently. All flash  
memory Erase and Program operations will automatically  
latch the input address and data signals and complete the  
operation in background without further input stimulus  
©2001 Silicon Storage Technology, Inc.  
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.  
ComboMemory are trademarks of Silicon Storage Technology, Inc.  
These specifications are subject to change without notice.  
S71137-03-000 10/01  
1
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