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SST31LF021E-300-4C-KH PDF预览

SST31LF021E-300-4C-KH

更新时间: 2024-09-28 20:07:51
品牌 Logo 应用领域
芯科 - SILICON 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
22页 224K
描述
Memory Circuit, Flash+SRAM, CMOS, PDSO32

SST31LF021E-300-4C-KH 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:TSSOP, TSSOP32,.56,20Reach Compliance Code:unknown
风险等级:5.85最长访问时间:300 ns
JESD-30 代码:R-PDSO-G32JESD-609代码:e0
内存集成电路类型:MEMORY CIRCUIT混合内存类型:FLASH+SRAM
端子数量:32最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP32,.56,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源:3.3 V认证状态:Not Qualified
最大待机电流:0.00003 A子类别:Other Memory ICs
最大压摆率:0.055 mA标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUALBase Number Matches:1

SST31LF021E-300-4C-KH 数据手册

 浏览型号SST31LF021E-300-4C-KH的Datasheet PDF文件第2页浏览型号SST31LF021E-300-4C-KH的Datasheet PDF文件第3页浏览型号SST31LF021E-300-4C-KH的Datasheet PDF文件第4页浏览型号SST31LF021E-300-4C-KH的Datasheet PDF文件第5页浏览型号SST31LF021E-300-4C-KH的Datasheet PDF文件第6页浏览型号SST31LF021E-300-4C-KH的Datasheet PDF文件第7页 
2 Megabit Flash + 1 Megabit SRAM ComboMemory  
SST31LF021E  
Advance Information  
FEATURES:  
Organized as 256K x8 Flash + 128K x8 SRAM  
Single 3.0-3.6V Read and Write Operations  
ConcurrentOperation  
Latched Address and Data for Flash  
1
FlashFastEraseandByte-Program:  
– Sector-Erase Time: 18 ms (typical)  
– Bank-Erase Time: 70 ms (typical)  
– Byte-Program Time: 14 µs (typical)  
– Bank Rewrite Time: 4 seconds (typical)  
– Read from or Write to SRAM while  
Erase/Program Flash  
2
Superior Reliability  
Flash Automatic Erase and Program Timing  
– Internal VPP Generation  
3
– Endurance: 100,000 Cycles (typical)  
– Greater than 100 years Data Retention  
FlashEnd-of-WriteDetection  
Low Power Consumption:  
– Toggle Bit  
– Data# Polling  
4
– Active Current: 10 mA (typical) for Flash  
and 20 mA (typical) for SRAM Read  
– Standby Current: 10 µA (typical)  
CMOS I/O Compatibility  
5
FlashSector-EraseCapability  
– Uniform 4 KByte sectors  
FastReadAccessTimes:  
JEDEC Standard Command Set  
Packages Available  
– 32-Pin TSOP (8mm x 13.4mm)  
6
– Flash: 300 ns  
– SRAM: 300 ns  
7
PRODUCTDESCRIPTION  
enable signals. The SRAM bank enable signal, BES#  
selects the SRAM bank and the flash memory bank  
enablesignal,BEF#selectstheflashmemorybank.The  
WE# signal has to be used with Software Data Protec-  
tion (SDP) command sequence when controlling the  
Erase and Program operations in the flash memory  
bank. The SDP command sequence protects the data  
stored in the flash memory bank from accidental alter-  
ation.  
The SST31LF021E device is a 256K x8 CMOS flash  
memory bank combined with a 128K x8 CMOS SRAM  
memorybankmanufacturedwithSST’sproprietary,high  
performance SuperFlash technology. Two pinout stan-  
dards are available for this device. The SST31LF021E  
conforms to standard EPROM pinouts. The  
SST31LF021E device writes (SRAM or flash) with a 3.0-  
3.6V power supply. The monolithic SST31LF021E de-  
vice conforms to Software Data Protect (SDP) com-  
mands for x8 EEPROMs.  
8
9
10  
11  
12  
13  
14  
15  
16  
The SST31LF021E provides the added functionality of  
being able to simultaneously read from or write to the  
SRAM bank while erasing or programming in the flash  
memory bank. The SRAM memory bank can be read or  
written while the flash memory bank performs Sector-  
Erase, Bank-Erase, or Byte-Program concurrently. All  
flash memory Erase and Program operations will auto-  
matically latch the input address and data signals and  
complete the operation in background without further  
input stimulus requirement. Once the internally con-  
trolled Erase or Program cycle in the flash bank has  
commenced,theSRAMbankcanbeaccessedforRead  
or Write.  
Featuring high performance Byte-Program, the flash  
memory bank provides a maximum Byte-Program time  
of 20 µsec. The entire flash memory bank can be erased  
and programmed byte-by-byte in typically 4 seconds,  
when using interface features such as Toggle Bit or  
Data# Polling to indicate the completion of Program  
operation. To protect against inadvertent flash write, the  
SST31LF021E device has on-chip hardware and Soft-  
ware Data Protection schemes. Designed, manufac-  
tured,andtestedforawidespectrumofapplications,the  
SST31LF021E device is offered with a guaranteed en-  
durance of 10,000 cycles. Data retention is rated at  
greater than 100 years.  
The SST31LF021E device is suited for applications that  
use both nonvolatile flash memory and volatile SRAM  
memory to store code or data. For all system applica-  
tions, the SST31LF021E device significantly improves  
performance and reliability, while lowering power con-  
sumption, when compared with multiple chip solutions.  
The SST31LF021E inherently uses less energy during  
Erase and Program than alternative flash technologies.  
The SST31LF021E operates as two independent  
memorybankswithrespectivebankenablesignals. The  
SRAM and Flash memory banks are superimposed in  
the same memory address space. Both memory banks  
share common address lines, data lines, WE# and OE#.  
The memory bank selection is done by memory bank  
© 2000 Silicon Storage Technology, Inc.  
371-02 2/00  
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. ComboMemory is a trademark of  
SiliconStorageTechnology,Inc.Thesespecificationsaresubjecttochangewithoutnotice.  

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