1 Megabit (128K x8) Page-Mode EEPROM
SST29EE010 / SST29LE010 / SST29VE010
Data Sheet
FEATURES:
•
Single Voltage Read and Write Operations
•
FastReadAccessTime
– 5.0V-only for the SST29EE010
– 3.0-3.6V for the SST29LE010
– 2.7-3.6V for the SST29VE010
– 5.0V-only operation: 90 and 120 ns
– 3.0-3.6V operation: 150 and 200 ns
– 2.7-3.6V operation: 200 and 250 ns
1
•
•
Superior Reliability
•
•
Latched Address and Data
2
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
Automatic Write Timing
– InternalVPPGeneration
End of Write Detection
Low Power Consumption
3
•
– Active Current: 20 mA (typical) for 5V and
10 mA (typical) for 3.0/2.7V
– Standby Current: 10 µA (typical)
– Toggle Bit
– Data# Polling
4
•
•
•
Hardware and Software Data Protection
•
FastPage-WriteOperation
TTL I/O Compatibility
– 128 Bytes per Page, 1024 Pages
– Page-Write Cycle: 5 ms (typical)
– Complete Memory Rewrite: 5 sec (typical)
– Effective Byte-Write Cycle Time: 39 µs
(typical)
5
JEDEC Standard
– Flash EEPROM Pinouts and command sets
Packages Available
•
6
– 32 Pin PDIP
– 32-Pin PLCC
– 32-Pin TSOP (8mm x 14mm, 8mm x 20mm)
7
PRODUCTDESCRIPTION
8
system applications, the SST29EE010/29LE010/
29VE010significantlyimproveperformanceandreliabil-
ity, while lowering power consumption. The
SST29EE010/29LE010/29VE010 improve flexibility
whileloweringthecostforprogram, data, andconfigura-
tion storage applications.
The SST29EE010/29LE010/29VE010 are 128K x8
CMOSPage-WriteEEPROMsmanufacturedwithSST’s
proprietary, high performance CMOS SuperFlash tech-
nology. The split-gate cell design and thick oxide tunnel-
ing injector attain better reliability and manufacturability
compared with alternate approaches. The
SST29EE010/29LE010/29VE010 write with a single
power supply. Internal Erase/Program is transparent to
the user. The SST29EE010/29LE010/29VE010
conform to JEDEC standard pinouts for byte-wide
memories.
9
10
11
12
13
14
15
16
To meet high density, surface mount requirements, the
SST29EE010/29LE010/29VE010 are offered in 32-pin
TSOP and 32-lead PLCC packages. A 600-mil, 32-pin
PDIP package is also available. See Figures 1 and 2 for
pinouts.
Featuring high performance Page-Write, the
SST29EE010/29LE010/29VE010provideatypicalByte-
Write time of 39 µsec. The entire memory, i.e., 128
KBytes, can be written page-by-page in as little as 5
seconds, when using interface features such as Toggle
Bit or Data# Polling to indicate the completion of a Write
cycle. To protect against inadvertent write, the
SST29EE010/29LE010/29VE010 have on-chip hard-
wareandSoftwareDataProtectionschemes.Designed,
manufactured,andtestedforawidespectrumofapplica-
tions, the SST29EE010/29LE010/29VE010 are offered
with a guaranteed Page-Write endurance of 104 cycles.
Data retention is rated at greater than 100 years.
DeviceOperation
TheSSTPage-ModeEEPROMoffersin-circuitelectrical
write capability. The SST29EE010/29LE010/29VE010
does not require separate Erase and Program opera-
tions. The internally timed write cycle executes both
erase and program transparently to the user. The
SST29EE010/29LE010/29VE010 have industry stan-
dard optional Software Data Protection, which SST
recommends always to be enabled. The SST29EE010/
29LE010/29VE010 are compatible with industry stan-
dard EEPROM pinouts and functionality.
Read
The SST29EE010/29LE010/29VE010 are suited for ap-
plicationsthatrequireconvenientandeconomicalupdat-
ing of program, configuration, or data memory. For all
The Read operations of the SST29EE010/29LE010/
29VE010 are controlled by CE# and OE#, both have to
be low for the system to obtain data from the outputs.
CE# is used for device selection. When CE# is high, the
©2000 SiliconStorageTechnology,Inc.TheSSTlogoandSuperFlashareregisteredtrademarksofSiliconStorageTechnology,Inc.
304-4 11/00 S71061
SSFisatrademarkofSiliconStorageTechnology,Inc.
Thesespecificationsaresubjecttochangewithoutnotice.
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