Datasheet > SSM2602CPZ-REEL1

SSM2602CPZ-REEL1

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
亚德诺 - ADI		解码器编解码器
页数	文件大小	规格书
28页	448K
描述
Low Power Audio Codec

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SSM2602CPZ-REEL1 数据手册

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SSM2602

Preliminary Technical Data

THEORY OF OPERATION

Decay (Gain Ramp-Up) Time

ADC HIGH-PASS FILTER

This is the time for the PGA gain to ramp up through 90% of its

range. The time for the recording level to return to its target value

therefore depends on both the decay time and the gain adjustment

required. If the gain adjustment is small, the time to return to

the target value will be less than the decay time.

DC offset can be removed by using the SSM2602 adjustable

digital high-pass filter (see Table 3 for characteristics).

Digital Filter Characteristics

The ADC and DAC employ separate digital filters.

AUTOMATIC LEVEL CONTROL (ALC)

Attack (Gain Ramp-Down) Time

Codec has an automatic level control that aims to keep a constant

recording volume irrespective of the input signal level. This is

achieved by continuously adjusting the PGA gain so that the

signal level at the ADC input remains constant. A digital peak

detector monitors the ADC output and changes the PGA gain if

necessary.

This is the time for the PGA gain to ramp down through 90% of

its range. The time for the recording level to return to its target

value therefore depends on both the attack time and the gain

adjustment required. If the gain adjustment is small, the time

to return to the target value will be less than the attack time.

INPUT SIGNAL

PGA

SIGNAL

AFTER

ALC

ALC TARGET

VALUE

DECAY TIME

ATTACK TIME

Figure 13. PGA and ALC Decay Time and Attack Time Definitions

Rev. PrB | Page 10 of 28

1...7 8 91011 12 13...28

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STM32F103C8T6 替代型号

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