Datasheet > SPT9689AIJ

SPT9689AIJ

更新时间： 2023-04-15 00:00:00

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		/
页数	文件大小	规格书
8页	85K
描述
Comparator, 2 Func, 15000uV Offset-Max, 0.65ns Response Time, BIPolar, CDIP16, SIDE BRAZED, DIP-16

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SPT9689AIJ 数据手册

SWITCHING TERMS (Refer to figure 1)

LATCH ENABLE TO OUTPUT LOW DELAY - The

propagationdelaymeasuredfromthe50%pointofthe

Latch Enable signal LOW to HIGH transition to the

50% point of an output HIGH to LOW transition

pLOL

INPUT TO OUTPUT HIGH DELAY - The propagation

delaymeasured fromthetimetheinputsignalcrosses

the reference (± the input offset voltage) to the 50%

point of an output LOW to HIGH transition

pdH

MINIMUM HOLD TIME - The minimum time after the

negative transition of the Latch Enable signal that the

input signal must remain unchanged in order to be

acquired and held at the outputs

INPUT TO OUTPUT LOW DELAY - The propagation

delay measured from the time the input signal crosses

the reference (± the input offset voltage) to the 50%

point of an output HIGH to LOW transition

pdL

MINIMUM LATCH ENABLE PULSE WIDTH - The

minimum time that the Latch Enable signal must be

HIGH in order to acquire an input signal change

LATCH ENABLE TO OUTPUT HIGH DELAY - The

propagationdelaymeasuredfromthe50%pointofthe

Latch Enable signal LOW to HIGH transition to 50%

point of an output LOW to HIGH transition

pLOH

MINIMUM SET-UP TIME - The minimum time before

the negative transition of the Latch Enable signal that

an input signal change must be present in order to be

acquired and held at the outputs

VOLTAGE OVERDRIVE - The difference between the

differential input and reference input voltages.

GENERAL INFORMATION

The SPT9689 is an ultrahigh speed dual voltage compara-

tor. It offers tight absolute characteristics. The device has

differential analog inputs and complementary logic outputs

compatiblewithECLsystems. Theoutputstageisadequate

for driving terminated 50 ohm transmission lines.

The negative common mode voltage is -2.5 V. The

positive common mode voltage is +4.0 V.

ThedualcomparatorssharethesameV andV connec-

tions but have separate grounds for each comparator to

achieve high crosstalk rejection.

The SPT9689 has a complementary latch enable control for

each comparator. Both should be driven by standard ECL

logic levels.

Figure 2 - Internal Function Diagram

–

PRE

AMP

ECL

OUT

LATCH

REF

CLK

BUF

GND

SPT9689

SPT

7/17/00

1 2 345 6 7 8

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