Datasheet > SPT9689AIJ

SPT9689AIJ

更新时间： 2023-04-15 00:00:00

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		/
页数	文件大小	规格书
8页	85K
描述
Comparator, 2 Func, 15000uV Offset-Max, 0.65ns Response Time, BIPolar, CDIP16, SIDE BRAZED, DIP-16

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SPT9689AIJ 数据手册

TEST LEVEL

TEST PROCEDURE

TEST LEVEL CODES

All electrical characteristics are subject to the

following conditions:

100% production tested at the specified temperature.

100% production tested at T =25 °C, and sample

tested at the specified temperatures.

All parameters having min/max specifications

are guaranteed. The Test Level column indi-

cates the specific device testing actually per-

formed during production and Quality Assur-

ance inspection. Any blank section in the data

column indicates that the specification is not

tested at the specified condition.

III

QA sample tested only at the specified temperatures.

Parameter is guaranteed (but not tested) by design

and characterization data.

Parameter is a typical value for information purposes

only.

100% production tested at T = 25 °C. Parameter is

guaranteed over specified temperature range.

The leading edge of the input signal (which consists of a

20 mV overdrive voltage) changes the comparator output

TIMING INFORMATION

after a time of t

or t

(Q or ). The input signal must be

pdH

pdL

The timing diagram for the comparator is shown in figure 1.

If LE is high and low in the SPT9689, the comparator

maintained for a time t (set-up time) before the LE falling

tracks the input difference voltage. When LE is driven low

and high, the comparator outputs are latched into their

edge and

rising edge and held for time t after the falling

edge for the comparator to accept data. After t , the output

ignores the input status until the latch is strobed again. A

minimum latch pulse width of t is needed for strobe

existing logic states.

operation, and the output transitions occur after a time of

or t

pLOH

pLOL

Figure 1 - Timing Diagram

Latch Enable

50%

t_H

tpL

t_S

Differential

Input Voltage

± V

REF

50%

t_pLOH

t _pdL

Output Q

t_pdH

t_pLOL

+=100 mV (p-p), V

=20 mV

The set-up and hold times are a measure of the time required for an input signal to propagate through the

first stage of the comparator to reach the latching circuitry. Input signals occurring before t will be detected

and held; those occurring after t will not be detected. Changes between t and t may not be detected.

SPT9689

SPT

7/17/00

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