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SNJ54LV20AFK PDF预览

SNJ54LV20AFK

更新时间: 2024-10-31 23:03:19
品牌 Logo 应用领域
德州仪器 - TI 输入元件
页数 文件大小 规格书
13页 330K
描述
DUAL 4 INPUT POSITIVE NAND GATE

SNJ54LV20AFK 技术参数

生命周期:Obsolete零件包装代码:QLCC
包装说明:QCCN, LCC20,.35SQ针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.84系列:LV/LV-A/LVX/H
JESD-30 代码:S-CQCC-N20长度:8.89 mm
负载电容(CL):50 pF逻辑集成电路类型:NAND GATE
最大I(ol):0.006 A功能数量:2
输入次数:4端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:QCCN
封装等效代码:LCC20,.35SQ封装形状:SQUARE
封装形式:CHIP CARRIER包装方法:TUBE
电源:3.3 VProp。Delay @ Nom-Sup:11.5 ns
传播延迟(tpd):18.5 ns认证状态:Not Qualified
施密特触发器:NO筛选级别:MIL-PRF-38535
座面最大高度:2.03 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:NO LEAD端子节距:1.27 mm
端子位置:QUAD宽度:8.89 mm
Base Number Matches:1

SNJ54LV20AFK 数据手册

 浏览型号SNJ54LV20AFK的Datasheet PDF文件第2页浏览型号SNJ54LV20AFK的Datasheet PDF文件第3页浏览型号SNJ54LV20AFK的Datasheet PDF文件第4页浏览型号SNJ54LV20AFK的Datasheet PDF文件第5页浏览型号SNJ54LV20AFK的Datasheet PDF文件第6页浏览型号SNJ54LV20AFK的Datasheet PDF文件第7页 
ꢀꢁꢂ ꢃ ꢄꢅꢆ ꢇ ꢈꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆꢇ ꢈ  
ꢋꢌꢈ ꢄ ꢃ ꢍꢎꢁ ꢏꢌꢐ ꢏꢑ ꢀꢎ ꢐ ꢎꢅꢒ ꢍꢁꢈꢁ ꢋ ꢓ ꢈꢐꢒ  
SCES339E − SEPTEMBER 2000 − REVISED APRIL 2005  
SN54LV20A . . . J OR W PACKAGE  
SN74LV20A . . . D, DB, DGV, NS, OR PW PACKAGE  
(TOP VIEW)  
D
D
D
D
D
D
D
2-V to 5.5-V V  
Operation  
CC  
Max t of 6 ns at 5 V  
pd  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
= 3.3 V, T = 25°C  
1A  
1B  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
A
2D  
2C  
NC  
Typical V  
>2.3 V at V  
(Output V  
Undershoot)  
OHV  
CC  
OH  
NC  
1C  
= 3.3 V, T = 25°C  
A
I
Supports Partial-Power-Down Mode  
off  
1D  
10 2B  
Operation  
9
8
1Y  
2A  
2Y  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
GND  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
SN54LV20A . . . FK PACKAGE  
(TOP VIEW)  
− 1000-V Charged-Device Model (C101)  
description/ordering information  
3
2
1
20 19  
18  
2C  
NC  
NC  
NC  
NC  
1C  
NC  
1D  
4
5
6
7
8
These dual 4-input positive-NAND gates are  
17  
16  
designed for 2-V to 5.5-V V  
operation.  
CC  
15 NC  
14  
9 10 11 12 13  
The ’LV20A devices perform the Boolean function  
Y = A B C D or Y = A + B + C + D in positive  
logic.  
2B  
These devices are fully specified for  
partial-power-down applications using I . The I  
off  
off  
NC − No internal connection  
circuitry disables the outputs, preventing  
damaging current backflow through the devices  
when they are powered down.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
Tube of 50  
SN74LV20AD  
SOIC − D  
LV20A  
Reel of 2500  
Reel of 2000  
Reel of 2000  
Tube of 90  
SN74LV20ADR  
SN74LV20ANSR  
SN74LV20ADBR  
SN74LV20APW  
SN74LV20APWR  
SN74LV20APWT  
SN74LV20ADGVR  
SNJ54LV20AJ  
SOP − NS  
74LV20A  
LV20A  
SSOP − DB  
−40°C to 85°C  
Reel of 2000  
Reel of 250  
Reel of 2000  
Tube of 25  
TSSOP − PW  
LV20A  
TVSOP − DGV  
CDIP − J  
LV20A  
SNJ54LV20AJ  
SNJ54LV20AW  
SNJ54LV20AFK  
−55°C to 125°C CFP − W  
Tube of 150  
Tube of 55  
SNJ54LV20AW  
SNJ54LV20AFK  
LCCC − FK  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2005, Texas Instruments Incorporated  
ꢌ ꢁ ꢄꢒꢀꢀ ꢑ ꢐꢔ ꢒꢕꢖ ꢎꢀ ꢒ ꢁ ꢑꢐꢒꢋ ꢗꢘ ꢙꢚ ꢛꢜꢝ ꢞꢟꢠ ꢡꢗ ꢝꢜ ꢡꢗꢢ ꢙꢡꢚ ꢏꢕ ꢑ ꢋ ꢌ ꢣꢐ ꢎꢑ ꢁ  
ꢙꢡ  
ꢤꢙ  
ꢐꢠꢪ  
ꢠꢡ  
ꢦꢢ ꢥ ꢢ ꢟ ꢠ ꢗ ꢠ ꢥ ꢚ ꢩ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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