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SNJ54LS165AFKA PDF预览

SNJ54LS165AFKA

更新时间: 2024-11-20 05:16:55
品牌 Logo 应用领域
德州仪器 - TI 移位寄存器
页数 文件大小 规格书
15页 372K
描述
PARALLEL-LOAD 8-BIT SHIFT REGISTERS

SNJ54LS165AFKA 数据手册

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SN54165, SN54LS165A, SN74165, SN74LS165A  
PARALLEL-LOAD 8-BIT SHIFT REGISTERS  
The SN54165 and SN74165 devices  
are obsolete and are no longer supplied.  
SDLS062D – OCTOBER 1976 – REVISED FEBRUARY 2002  
SN54165, SN54LS165A . . . J OR W PACKAGE  
SN74165 . . . N PACKAGE  
Complementary Outputs  
Direct Overriding Load (Data) Inputs  
Gated Clock Inputs  
SN74LS165A . . . D, N, OR NS PACKAGE  
(TOP VIEW)  
Parallel-to-Serial Data Conversion  
SH/LD  
CLK  
E
V
CC  
CLK INH  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
TYPICAL MAXIMUM  
CLOCK FREQUENCY POWER DISSIPATION  
TYPICAL  
TYPE  
’165  
D
C
B
A
26 MHz  
35 MHz  
210 mW  
90 mW  
F
G
H
’LS165A  
description  
Q
SER  
H
GND  
Q
H
The ’165 and ’LS165A are 8-bit serial shift  
registers that shift the data in the direction of Q  
A
toward Q when clocked. Parallel-in access to  
H
SN54LS165A . . . FK PACKAGE  
(TOP VIEW)  
each stage is made available by eight individual,  
direct data inputs that are enabled by a low level  
at the shift/load (SH/LD) input. These registers  
also feature gated clock (CLK) inputs and  
complementary outputs from the eighth bit. All  
inputs  
are  
diode-clamped  
to minimize  
3
2
1
20 19  
18  
transmission-line effects, thereby simplifying  
system design.  
4
5
6
7
8
D
C
NC  
B
A
E
F
NC  
G
17  
16  
15  
14  
Clocking is accomplished through a two-input  
positive-NOR gate, permitting one input to be  
used as a clock-inhibit function. Holding either of  
the clock inputs high inhibits clocking, and holding  
either clock input low with SH/LD high enables the  
other clock input. Clock inhibit (CLK INH) should  
be changed to the high level only while CLK is  
high. Parallel loading is inhibited as long asSH/LD  
is high. Data at the parallel inputs are loaded  
directly into the register while SH/LD is low,  
independently of the levels of CLK, CLK INH, or  
serial (SER) inputs.  
H
9 10 11 12 13  
NC – No internal connection  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2002, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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