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SNJ54ALVTH16260WD PDF预览

SNJ54ALVTH16260WD

更新时间： 2024-11-22 23:34:03
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其他 - ETC 信息通信管理
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12页 207K
描述
Bus Exchanger

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SNJ54ALVTH16260WD 数据手册

 浏览型号SNJ54ALVTH16260WD的Datasheet PDF文件第2页浏览型号SNJ54ALVTH16260WD的Datasheet PDF文件第3页浏览型号SNJ54ALVTH16260WD的Datasheet PDF文件第4页浏览型号SNJ54ALVTH16260WD的Datasheet PDF文件第5页浏览型号SNJ54ALVTH16260WD的Datasheet PDF文件第6页浏览型号SNJ54ALVTH16260WD的Datasheet PDF文件第7页 
SN54ALVTH16260, SN74ALVTH16260  
2.5-V/3.3-V 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH  
WITH 3-STATE OUTPUTS  
SCES332 – APRIL 2000  
SN54ALVTH16260 . . . WD PACKAGE  
SN74ALVTH16260 . . . DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Widebus Design for  
2.5-V and 3.3-V Operation and Low  
Static-Power Dissipation  
OEA  
LE1B  
2B3  
GND  
2B2  
OE2B  
LEA2B  
2B4  
GND  
2B5  
1
2
3
4
5
6
7
8
9
56  
55  
54  
53  
52  
51  
50  
49  
48  
Support Mixed-Mode Signal Operation (5-V  
Input and Output Voltages With 2.3-V to  
3.6-V V  
)
CC  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
2B1  
2B6  
= 3.3 V, T = 25°C  
A
V
V
CC  
CC  
High-Drive (–24 mA/24 mA at 2.5-V and  
–32/64mA at 3.3-V V  
A1  
A2  
2B7  
2B8  
)
CC  
I
and Power-Up 3-State Support Hot  
off  
A3 10  
47 2B9  
Insertion  
GND  
A4  
GND  
2B10  
11  
12  
46  
45  
Use Bus Hold on Data Inputs in Place of  
External Pullup/Pulldown Resistors to  
Prevent the Bus From Floating  
A5 13  
A6 14  
44 2B11  
43 2B12  
42 1B12  
41 1B11  
40 1B10  
39 GND  
38 1B9  
37 1B8  
36 1B7  
Auto3-State Eliminates Bus Current  
A7 15  
Loading When Output Exceeds V  
+ 0.5 V  
CC  
A8 16  
Flow-Through Architecture Facilitates  
Printed Circuit Board Layout  
A9 17  
GND 18  
A10 19  
A11 20  
A12 21  
Distributed V  
High-Speed Switching Noise  
and GND Pins Minimize  
CC  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL), Thin Shrink  
Small-Outline (DGG), Thin Very  
Small-Outline (DGV) Packages, and 380-mil  
Fine-Pitch Ceramic Flat (WD) Package  
V
22  
35  
V
CC  
CC  
1B1 23  
1B2 24  
GND 25  
1B3 26  
LE2B 27  
SEL 28  
34 1B6  
33 1B5  
32 GND  
31 1B4  
NOTE: For tape and reel order entry:  
30 LEA1B  
29 OE1B  
The DGGR package is abbreviated to GR, and  
the DGVR package is abbreviated to VR.  
description  
The ’ALVTH16260 devices are 12-bit to 24-bit multiplexed D-type latches designed for 2.5-V or 3.3-V V  
operation, but with the capability to provide a TTL interface to a 5-V system environment.  
CC  
Three 12-bit I/O ports (A1–A12, 1B1–1B12, and 2B1–2B12) are available for address and/or data transfer. The  
output-enable (OE1B, OE2B, and OEA) inputs control the bus transceiver functions. The OE1B and OE2B  
control signals also allow bank control in the A-to-B direction.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
Copyright 2000, Texas Instruments Incorporated  
PRODUCT PREVIEW information concerns products in the formative or  
design phase of development. Characteristic data and other  
specifications are design goals. Texas Instruments reserves the right to  
change or discontinue these products without notice.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...12

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