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SNJ54ACT1284FK

更新时间： 2024-11-18 05:04:39
品牌 Logo 应用领域
德州仪器 - TI 输出元件
页数 文件大小 规格书
12页 287K
描述
7-BIT BUS INTERFACES WITH 3-STATE OUTPUTS

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SNJ54ACT1284FK 数据手册

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SCAS459D − NOVEMBER 1994 − REVISED OCTOBER 2003  
SN54ACT1284 . . . J OR W PACKAGE  
SN74ACT1284 . . . DB, DW, NS, OR PW PACKAGE  
(TOP VIEW)  
D
D
D
D
D
D
D
4.5-V to 5.5-V V  
Operation  
CC  
Inputs Accept Voltages to 5.5 V  
Max t of 20 ns at 5 V  
pd  
3-State Outputs Directly Drive Bus Lines  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
A1  
A2  
A3  
B1  
B2  
B3  
B4  
Flow-Through Architecture Optimizes PCB  
Layout  
A4  
Center-Pin V  
and GND Configurations  
CC  
GND  
GND  
A5  
A6  
A7  
V
V
CC  
CC  
Minimize High-Speed Switching Noise  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
B5  
B6  
B7  
HD  
D
Designed for the IEEE 1284-I (Level-1 Type)  
and IEEE 1284-II (Level-2 Type) Electrical  
Specifications  
DIR  
SN54ACT1284 . . . FK PACKAGE  
(TOP VIEW)  
description/ordering information  
The ’ACT1284 devices are designed for  
asynchronous two-way communication between  
data buses. The control function minimizes  
external timing requirements.  
3
2
1 20 19  
18  
B3  
B4  
V
A4  
GND  
GND  
A5  
4
5
6
7
8
17  
16  
15  
14  
CC  
The devices allow data transmission in either the  
A-to-B or the B-to-A direction for bits 1, 2, 3, and  
4, depending on the logic level at the  
direction-control (DIR) input. Bits 5, 6, and 7,  
however, always transmit in the A-to-B direction.  
V
CC  
B5  
A6  
9 10 11 12 13  
The output drive for each mode is determined by the high-drive (HD) control pin. When HD is high, the high drive  
is delivered by the totem-pole configuration, and when HD is low, the outputs are open drain. This meets the  
drive requirements as specified in the IEEE 1284-I (level-1 type) and the IEEE 1284-II (level-2 type) parallel  
peripheral-interface specification.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
Tube  
SN74ACT1284DW  
SN74ACT1284DWR  
SN74ACT1284NSR  
SN74ACT1284DBR  
SN74ACT1284PW  
SN74ACT1284PWR  
SNJ54ACT1284J  
SOIC − DW  
ACT1284  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SOP − NS  
ACT1284  
AU284  
0°C to 70°C  
SSOP − DB  
TSSOP − PW  
AU284  
Tape and reel  
Tube  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54ACT1284J  
SNJ54ACT1284W  
SNJ54ACT1284FK  
Tube  
SNJ54ACT1284W  
SNJ54ACT1284FK  
−55°C to 125°C  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...12

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