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SN75164B

更新时间： 2024-11-20 12:21:43
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德州仪器 - TI 总线收发器
页数 文件大小 规格书
12页 230K
描述
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER

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SN75164B 数据手册

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SN75164B  
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER  
SLLS011A – OCTOBER 1985 – REVISED FEBRUARY 1993  
8-Channel Bidirectional Transceiver  
N PACKAGE  
(TOP VIEW)  
Power-Up/Power-Down Protection  
(Glitch Free)  
ATN+EOI (OR Function) Output to Simplify  
Board Layout  
SC  
TE  
1
V
CC  
ATN + EOI  
REN  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
2
3
REN  
IFC  
Designed to Implement Control Bus  
Interface for Multiple Controllers  
4
IFC  
5
NDAC  
NRFD  
DAV  
EOI  
NDAC  
NRFD  
Low-Power Dissipation . . . 72 mW Max Per  
Channel  
6
GPIB  
I/O Ports  
Terminal  
I/O Ports  
7
DAV  
EOI  
ATN  
SRQ  
DC  
Fast Propagation Times . . . 22 ns Max  
High-impedance PNP Inputs  
8
9
ATN  
Receiver Hysteresis . . . 650 mV Typ  
10  
11  
SRQ  
GND  
Bus-Terminating Resistors Provided on  
Driver Outputs  
NC – No internal connection  
No Loading of Bus When Device Is  
Powered Down (V  
= 0)  
CC  
NOT RECOMMENDED FOR NEW DESIGN  
description  
CHANNEL IDENTIFICATION TABLE  
The SN75164B eight-channel general-purpose  
interface bus transceiver is monolithic,  
high-speed, low-power Schottky device designed  
to meet the requirements of IEEE Standard  
488-1978. Each transceiver is designed to  
provide the bus-management and data-transfer  
NAME  
IDENTITY  
CLASS  
a
DC  
TE  
SC  
Direction Control  
Talk Enable  
System Control  
Control  
ATN  
SRQ  
REN  
IFC  
Attention  
Service Request  
Remote Enable  
Interface Clear  
End or Identify  
Bus  
Management  
signals between operating units of  
a
multiple-controller instrumentation system. When  
combined with the SN75160B octal bus  
transceiver, the SN75164B provides the complete  
16-wire interface for the IEEE-488 bus.  
EOI  
ATN Logical or EOI  
Logic  
ATN + EOI  
DAV  
NDAC  
NRFD  
Data Valid  
Not Data Accepted  
Not Ready for Data  
Data  
Transfer  
The SN75164B features eight driver-receiver  
pairs connected in a front-to-back configuration to  
form input/output (I/O) ports at both the bus and terminal sides. All outputs are disabled (at a high-impedance  
state) during V  
power-up and power-down transitions for glitch-free operation. The direction of data flow  
CC  
through these driver-receiver pairs is determined by the DC, TE, and SC enable signals. The SN75164B is  
identical to the SN75162B with the addition of an OR gate to help simplify board layouts in several popular  
applications. The ATN and EOI signals are ORed to pin 21, which is a standard totem-pole output.  
Copyright 1993, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...12

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